74ALVC573BQ ,Octal D-type transparent latch; 3-stateLogic diagram (one latch)D0 D1 D2 D3 D4 D5 D6 D7D Q D Q D Q D Q D Q D Q D Q D QLATCH LATCH LATCH LA ..
74ALVC573BQ ,Octal D-type transparent latch; 3-stateINTEGRATED CIRCUITSDATA SHEET74ALVC573Octal D-type transparent latch;3-stateProduct specification 20 ..
74ALVC573BQ ,Octal D-type transparent latch; 3-stateFeatures■ Wide supply voltage range from 1.65 V to 3.6 V■ 3.6 V tolerant inputs/outputs■ CMOS low p ..
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74ALVC573BQ-74ALVC573PW
Octal D-type transparent latch; 3-state
General descriptionThe 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for
each latch and 3-state true outputsfor bus-oriented applications.A latch enable (LE) input
and an outputs enable (OE) input are common to all latches.
When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this
condition, the latches are transparent, that is, a latch output will change each time its
corresponding D-input changes. When pin LE is LOW, the latches store the information
that was presentat the D-inputs one set-up time preceding the HIGH-to-LOW transitionof
pin LE.
When pin OEis LOW, the contentsof the eight latches are availableat the Q-outputs (pins
Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of input pin OE does not affect the state of the latches.
The 74ALVC573 is functionally identical to the 74ALVC373, but has a different pin
arrangement.
Features Wide supply voltage range from 1.65 V to 3.6V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95V) JESD8-5 (2.3 V to 2.7V) JESD8B/JESD36 (2.7 V to 3.6V) ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A 115-A exceeds 200V
74AL VC573
Octal D-type transparent latch; 3-state
Rev. 03 — 26 October 2007 Product data sheet
NXP Semiconductors 74AL VC573
Octal D-type transparent latch; 3-state Ordering information Functional diagram
Table 1. Ordering information74ALVC573D −40 °Cto+85°C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74ALVC573PW −40 °Cto+85°C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74ALVC573BQ −40 °Cto+85°C DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5× 4.5× 0.85 mm
SOT764-1
NXP Semiconductors 74AL VC573
Octal D-type transparent latch; 3-state
NXP Semiconductors 74AL VC573
Octal D-type transparent latch; 3-state Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin descriptionD[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input 11 latch enable input (active HIGH) 1 output enable input (active LOW)
Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state latch output
VCC 20 supply voltage
GND 10 ground (0V)
NXP Semiconductors 74AL VC573
Octal D-type transparent latch; 3-state Functional description[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = High-impedance OFF-state
Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
[3] For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.
Table 3. Functional table[1]Enable and read register
(transparent mode) LLL HHHH
Latch and read register L L l L L
LLhH H
Latch register and disable
outputs l L Z LhH Z
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground=0V).
VCC supply voltage −0.5 +4.6 V
IIK input clamping current VI <0V −50 - mA input voltage −0.5 +4.6 V
IOK output clamping current VO >VCC or VO <0V - ±50 mA output voltage output HIGH or LOW state [1][2] −0.5 VCC+ 0.5 V
output 3-state −0.5 +4.6 V
power-down mode, VCC = 0V [2] −0.5 +4.6 V output current VO=0 V to VCC - ±50 mA
ICC supply current - 100 mA
IGND ground current −100 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb= −40 °C to +85°C [3] - 500 mW
NXP Semiconductors 74AL VC573
Octal D-type transparent latch; 3-state Recommended operating conditions Static characteristics
Table 5. Recommended operating conditionsVCC supply voltage 1.65 3.6 V input voltage 0 3.6 V output voltage output HIGH or LOW state 0 VCC V
output 3-state 0 3.6 V
power-down mode; VCC=0V 0 3.6 V
Tamb ambient temperature in free air −40 +85 °C
Δt/ΔV input transition rise and fall rate VCC= 1.65 V to 2.7V - 20 ns/V
VCC= 2.7 V to 3.6V - 10 ns/V
Table 6. Static characteristicsAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 × VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VOH HIGH-level output voltage VI =VIHorVIL= −100 μA; VCC= 1.65Vto 3.6V VCC− 0.2 - - V=−6 mA; VCC = 1.65 V 1.25 - - V= −12 mA; VCC = 2.3V 1.8 - - V= −18 mA; VCC = 2.3V 1.7 - - V= −12 mA; VCC = 2.7 V 2.2 - - V= −18 mA; VCC = 3.0 V 2.4 - - V= −24 mA; VCC = 3.0 V 2.2 - - V
VOL LOW-level output voltage VI =VIHorVIL= 100 μA; VCC= 1.65Vto 3.6 V - - 0.2 V=6 mA; VCC = 1.65 V - - 0.3 V=12 mA; VCC = 2.3V - - 0.4 V=18 mA; VCC = 2.3V - - 0.6 V=12 mA; VCC = 2.7 V - - 0.4 V=18 mA; VCC = 3.0V - - 0.4 V=24 mA; VCC = 3.0 V - - 0.55 V input leakage current VCC = 3.6 V; VI= 3.6Vor GND - ±0.1 ±5 μA
NXP Semiconductors 74AL VC573
Octal D-type transparent latch; 3-state[1] All typical values are measured at VCC=3.3 V (unless stated otherwise) and Tamb =25°C.
10. Dynamic characteristicsIOZ OFF-state output current VI =VIHor VIL; VCC= 1.65 V to 3.6V;= 3.6Vor GND; ±0.1 ±10 μA
IOFF power-off leakage supply VCC = 0 V; VIorVO = 0 V to 3.6V - ±0.1 ±10 μA
ICC supply current VCC = 3.6 V; VI =VCCor GND; =0A 0.2 10 μA
ΔICC additional supply current per input pin; VCC= 3.0Vto 3.6 V; =VCC− 0.6 V; IO =0A 5 750 μA input capacitance - 3.5 - pF
Table 6. Static characteristics …continuedAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristicsVoltages are referenced to GND (ground=0 V). For test circuit see Figure 12.
tpd propagation delay Dnto Qn; see Figure8 [2]
VCC = 1.65 V to 1.95 V 1.0 2.5 5.4 ns
VCC = 2.3Vto 2.7V 1.0 2.0 3.5 ns
VCC = 2.7 V 1.0 2.3 3.6 ns
VCC = 3.0 V to 3.6 V 1.0 2.2 3.3 nsto Qn; see Figure9
VCC = 1.65 V to 1.95 V 1.0 2.8 6.0 ns
VCC = 2.3Vto 2.7V 1.0 2.1 3.8 ns
VCC = 2.7 V 1.0 2.4 3.7 ns
VCC = 3.0 V to 3.6 V 1.0 2.3 3.3 ns
ten enable time OEto Qn; see Figure10 [2]
VCC = 1.65 V to 1.95 V 1.5 3.0 6.4 ns
VCC = 2.3Vto 2.7V 1.0 2.4 4.5 ns
VCC = 2.7 V 1.5 3.0 4.6 ns
VCC = 3.0 V to 3.6 V 1.0 2.3 4.0 ns
tdis disable time OEto Qn; see Figure10 [2]
VCC = 1.65 V to 1.95 V 1.5 3.4 7.0 ns
VCC = 2.3Vto 2.7V 1.0 2.2 4.4 ns
VCC = 2.7 V 1.5 2.8 4.4 ns
VCC = 3.0 V to 3.6 V 1.0 2.7 4.4 ns
NXP Semiconductors 74AL VC573
Octal D-type transparent latch; 3-state[1] Typical values are measured at Tamb =25°C
[2] tpd is the same as tPHL and tPLH.
ten is the same as tPZH and tPZL.
tdis is the same as tPHZ and tPLZ.
[3] CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where: = input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in Volts= number of inputs switching
Σ(CL× VCC2×fo)= sum of the outputs pulse width LE pulse width HIGH; see Figure9
VCC = 1.65 V to 1.95 V 3.8 - - ns
VCC = 2.3Vto 2.7V 3.3 - - ns
VCC = 2.7 V 3.3 - - ns
VCC = 3.0 V to 3.6 V 3.3 - - ns
tsu set-up time Dnto LE; see Figure11
VCC = 1.65 V to 1.95 V 0.8 - - ns
VCC = 2.3Vto 2.7V 0.8 - - ns
VCC = 2.7 V 0.8 - - ns
VCC = 3.0 V to 3.6 V 0.8 - - ns hold time Dnto LE; see Figure11
VCC = 1.65 V to 1.95 V 0.8 - - ns
VCC = 2.3Vto 2.7V 0.8 - - ns
VCC = 2.7 V 0.8 - - ns
VCC = 3.0 V to 3.6 V 0.7 - - ns
CPD power dissipation
capacitance
per latch; VI = GND to VCC; VCC = 3.3V [3]
outputs HIGH or LOW state - 37 - pF
outputs 3-state - 7 - pF
Table 7. Dynamic characteristics …continuedVoltages are referenced to GND (ground=0 V). For test circuit see Figure 12.
NXP Semiconductors 74AL VC573
Octal D-type transparent latch; 3-state
11. Waveforms
Table 8. Measurement points1.65 V to 1.95V 0.5VCC VOL + 0.15V VOH − 0.15V
2.3 V to 2.7V 0.5VCC VOL + 0.15V VOH − 0.15V
2.7V 1.5 V VOL + 0.3V VOH − 0.3V
3.0 V to 3.6V 1.5 V VOL + 0.3V VOH − 0.3V
