74ALVC38MTCX ,Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and OutputsElectrical CharacteristicsVCCSymbol Parameter Conditions Min Max Units (V)V HIGH Level Input Voltag ..
74ALVC38MTCX ,Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputsapplications with I/O compatibility up toCC
74ALVC38MTCX-74ALVC38MX
Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs
74ALVC38 Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs December 2001 Revised March 2005 74ALVC38 Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs General Description Features The ALVC38 contains four 2-input NAND gates with open1.4V to 3.6V V supply operation CC drain outputs. This product is designed for low voltage 3.6V tolerant inputs and outputs (1.4V to 3.6V) V applications with I/O compatibility up to CC t PD 3.6V. 3.3 ns max for 3.0V to 3.6V V CC The ALVC38 is fabricated with advanced CMOS technol- ogy to achieve high-speed operation while maintaining 4.2 ns max for 2.3V to 2.7V V CC CMOS low power dissipation. 6.7 ns max for 1.65V to 1.95V V CC Power-off high impedance inputs and outputs Uses patented Quiet Series¥ noise/EMI reduction circuitry Latchup conforms to JEDEC JED78 ESD performance: Human body model ! 2000V Machine model ! 250V Ordering Code: Order Number Package Number Package Description 74ALVC38M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ALVC38MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description A , B Inputs n n O Outputs n Quiet Series¥ is a trademark of . © 2005 DS500719
