74ALVC16500MTDX ,Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and OutputsFeaturesThe ALVC16500 is an 18-bit universal bus transceiver
74ALVC16500MTDX
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
74ALVC16500 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs October 2001 Revised October 2001 74ALVC16500 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs General Description Features The ALVC16500 is an 18-bit universal bus transceiver1.65V–3.6V V supply operation CC which combines D-type latches and D-type flip-flops to 3.6V tolerant inputs and outputs allow data flow in transparent, latched, and clocked modes. t (A to B, B to A) PD Data flow in each direction is controlled by output-enable 3.4 ns max for 3.0V to 3.6V V CC (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the 4.0 ns max for 2.3V to 2.7V V CC device operates in the transparent mode when LEAB is 7.0 ns max for 1.65V to 1.95V V CC HIGH. When LEAB is LOW, the A data is latched if CLKAB Power-off high impedance inputs and outputs is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOWSupports live insertion/withdrawal (Note 1) transition of CLKAB. When OEAB is HIGH, the outputs are Uses patented noise/EMI reduction circuitry active. When OEAB is LOW, the outputs are in a high- Latchup conforms to JEDEC JED78 impedance state. ESD performance: Data flow for B to A is similar to that of A to B but uses Human body model > 2000V OEBA, LEBA, and CLKBA. The output enables are com- plementary (OEAB is active HIGH and OEBA is active Machine model >200V LOW). Note 1: To ensure the high-impedance state during power up or power down, OEBA should be tied to V through a pull-up resistor and OEAB The ALVC16500 is designed for low voltage (1.65V to CC should be tied to GND through a pull-down resistors; the minimum value of 3.6V) V applications with I/O capability up to 3.6V. CC the resistor is determined by the current-sourcing capability of the driver. The 74ALVC16500 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation. Ordering Code: Order Number Package Number Package Description 74ALVC16500MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 DS500684
