74ALVC16373MTD ,Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputsapplications with I/O compatibility up to 3.6V.CC
74ALVC16373MTD
Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
74ALVC16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs October 2001 Revised October 2001 74ALVC16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs General Description Features The ALVC16373 contains sixteen non-inverting latches1.1V to 3.6V V supply operation CC with 3-STATE outputs and is intended for bus oriented 3.6V tolerant inputs and outputs applications. The device is byte controlled. The flip-flops t (I to O ) PD n n appear to be transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets 3.5 ns max for 3.0V to 3.6V V CC the setup time is latched. Data appears on the bus when 3.9 ns max for 2.3V to 2.7V V CC the Output Enable (OE) is LOW. When OE is HIGH, the 6.8 ns max for 1.65V to 1.95V V outputs are in a high impedance state. CC Power-off high impedance inputs and outputs The 74ALVC16373 is designed for low voltage (1.1V to 3.6V) V applications with I/O compatibility up to 3.6V. CCSupport live insertion and withdrawal (Note 1) The 74ALVC16373 is fabricated with an advanced CMOSUses patented noise/EMI reduction circuitry technology to achieve high speed operation while maintain-Latchup conforms to JEDEC JED78 ing low CMOS power dissipation. ESD performance: Human body model > 2000V Machine model > 200V Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up resistor; the minimum CC value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74ALVC16373GX BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 2) (Preliminary) [TAPE and REEL] 74ALVC16373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 3) Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2001 DS500687
