74ALVC162839TX ,Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs and 26 Ohm Series Resistors in the Outputsapplications such as memory address drivers, clock driv-
74ALVC162839T-74ALVC162839TX
Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs and 26 Ohm Series Resistors in the Outputs
74ALVC162839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in the Outputs November 2001 Revised November 2001 74ALVC162839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in the Outputs General Description Features The ALVC162839 contains twenty non-inverting selectableCompatible with PC100 and PC133 DIMM module buffered or registered paths. The device can be configured specifications to operate in a registered, or flow through buffer mode by1.65V–3.6V V supply operation CC utilizing the register enable (REGE) and Clock (CLK) sig- 3.6V tolerant inputs and outputs nals. The device operates in a 20-bit word wide mode. All 26Ω series resistors in the outputs outputs can be placed into 3-STATE through use of the OE pin. These devices are ideally suited for buffered or regis-t (CLK to O ) PD n tered 168 pin and 200 pin SDRAM DIMM memory mod- 4.6 ns max for 3.0V to 3.6V V CC ules. 6.3 ns max for 2.3V to 2.7V V CC The 74ALVC162839 is designed for low voltage (1.65V to 3.6V) V applications with I/O compatibility up to 3.6V. 9.8 ns max for 1.65V to 1.95V V CC CC The 74ALVC162839 is also designed with 26Ω seriesPower-off high impedance inputs and outputs resistors in the outputs. This design reduces line noise in Supports live insertion and withdrawal (Note 1) applications such as memory address drivers, clock driv- Uses patented noise/EMI reduction circuitry ers, and bus transceivers/transmitters. Latchup conforms to JEDEC JED78 The 74ALVC162839 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain-ESD performance: ing low CMOS power dissipation. Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up resistor; the minimum CC value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74ALVC162839T MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) I –I Inputs 0 19 O –O Outputs 0 19 CLK Clock Input REGE Register Enable Input © 2001 DS500712
