74ALVC162835 ,Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26-Ohm Series Resistors in Outputsapplications with I/O capability up to 3.6V.CCNote 1: To ensure the high impedance state during pow ..
74ALVC162835A ,18-bit registered driver with 30 Ohm termination resistors (3-State)
74ALVC162836ADGG ,20-bit registered driver with inverted register enable and 30 惟 termination resistors (3-state)
74ALVC162836ADGG ,20-bit registered driver with inverted register enable and 30 惟 termination resistors (3-state)
74ALVC162839T ,Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs and 26 Ohm Series Resistors in the OutputsFunctional DescriptionThe 74ALVC162839 consists of twenty selectable non-inverting buffers or regis ..
74ALVC162839TX ,Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs and 26 Ohm Series Resistors in the Outputsapplications such as memory address drivers, clock driv-
74ALVC162835
Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26-Ohm Series Resistors in Outputs
74ALVC162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in Outputs September 2001 Revised February 2002 74ALVC162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in Outputs General Description Features The ALVC162835 low voltage 18-bit universal bus driverCompatible with PC100 DIMM module specifications combines D-type latches and D-type flip-flops to allow data1.65V to 3.6V V specifications provided CC flow in transparent, latched and clocked modes. 3.6V tolerant inputs and outputs Data flow is controlled by output-enable (OE), latch-enable 26Ω series resistors in outputs (LE), and clock (CLK) inputs. The device operates in t (CLK to O ) Transparent Mode when LE is held HIGH. The device PD n operates in clocked mode when LE is LOW and CLK is tog- 5.4 ns max for 3.0V to 3.6V V CC gled. Data transfers from the Inputs (I ) to Outputs (O ) on n n 6.3 ns max for 2.3V to 2.7V V CC a Positive Edge Transition of the Clock. When OE is LOW, 9.2 ns max for 1.65V to 1.95V V CC the output data is enabled. When OE is HIGH the output Power-off high impedance inputs and outputs port is in a high impedance state. Supports live insertion/withdrawal (Note 1) The ALVC162835 is designed with 26Ω series resistors in Latchup conforms to JEDEC JED78 the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus trans-ESD performance: ceivers/transmitters. Human body model > 2000V The 74ALVC162835 is designed for low voltage (1.65V to Machine model >200V 3.6V) V applications with I/O capability up to 3.6V. CC Note 1: To ensure the high impedance state during power up or power down, OE should be tied to V through a pulldown resistor; the minimum The 74ALVC162835 is fabricated with an advanced CMOS CC value of the resistor is determined by the current sourcing capability of the technology to achieve high speed operation while maintain- driver. ing low CMOS power dissipation. Ordering Code: Package Order Number Package Description Number 74ALVC162835T MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2002 DS500646
