74ALVC00MTCX ,Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and OutputsFeaturesThe ALVC00 contains four 2-input NAND gates. This prod-
74ALVC00MTCX
Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs
74ALVC00 Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs September 2001 Revised February 2005 74ALVC00 Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs General Description Features The ALVC00 contains four 2-input NAND gates. This prod-1.65V to 3.6V V supply operation CC uct is designed for low voltage (1.65V to 3.6V) V applica- CC3.6V tolerant inputs and outputs tions with I/O compatibility up to 3.6V. t PD The ALVC00 is fabricated with an advanced CMOS tech- 3 ns max for 3.0V to 3.6V V CC nology to achieve high-speed operation while maintaining low CMOS power dissipation. 3.5 ns max for 2.3V to 2.7V V CC 4.4 ns max for 1.65V to 1.95V V CC Power-off high impedance inputs and outputs Uses patented Quiet Series¥ noise/EMI reduction circuitry Latchup conforms to JEDEC JED78 ESD performance: Human body model ! 2000V Machine model ! 250V Ordering Code: Order Number Package Number Package Description 74ALVC00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ALVC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description A , B Inputs n n O Outputs n Quiet Series¥ is a trademark of . © 2005 DS500626
