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Partno	Mfg	Dc	Qty	Available	Descript
74ALVC00D	PH	N/a	49	avai	Quad 2-input NAND gate
74ALVC00PW	NXP	N/a	6	avai	74ALVC00; Quad 2-input NAND gate

74ALVC00D ,Quad 2-input NAND gateLogic diagram for one gate5. Pinning information5.1 Pinning terminal 1index area2 131B 4B1A 1 14 VC ..
74ALVC00MTCX ,Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and OutputsFeaturesThe ALVC00 contains four 2-input NAND gates. This prod-

74ALVC00D-74ALVC00PW
Quad 2-input NAND gate
1. General description
The 74ALVC00 is a quad 2-input NAND gate.
Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.
2. Features and benefits Wide supply voltage range from 1.65 V to 3.6V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95V) JESD8-5 (2.3 V to 2.7V) JESD8B/JESD36 (2.7 V to 3.6V) ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V
3. Ordering information
74AL VC00
Quad 2-input NAND gate
Rev. 3 — 16 May 2014 Product data sheet
Table 1. Ordering information
NXP Semiconductors 74ALVC00
Quad 2-input NAND gate
4. Functional diagram
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
NXP Semiconductors 74ALVC00
Quad 2-input NAND gate
6. Functional description
[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
[3] For SO14 packages: above 70 C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.
Table 3. Function selection[1]
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground=0V).
NXP Semiconductors 74ALVC00
Quad 2-input NAND gate
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74ALVC00
Quad 2-input NAND gate
[1] All typical values are measured at VCC=3.3 V (unless stated otherwise) and Tamb =25C.
10. Dynamic characteristics
[1] Typical values are measured at Tamb =25C
[2] tpd is the same as tPHL and tPLH.
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where: = input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in Volts= number of inputs switching
(CL VCC2fo)= sum of the outputs
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground=0 V). For test circuit, see Figure7.
NXP Semiconductors 74ALVC00
Quad 2-input NAND gate
11. Waveforms
Table 8. Measurement points
NXP Semiconductors 74ALVC00
Quad 2-input NAND gate
Table 9. Test data

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