74ALS245 ,Octal 3-STATE Bus TransceiverFeaturesThis advanced low power Schottky device contains 8 pairs Advanced oxide-isolated, ion-impl ..
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74HC4053D ,Triple 2-channel analog multiplexer/demultiplexerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
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74ALS245
Octal 3-STATE Bus Transceiver
DM74ALS245A Octal 3-STATE Bus Transceiver September 1986 Revised February 2000 DM74ALS245A Octal 3-STATE Bus Transceiver General Description Features This advanced low power Schottky device contains 8 pairs � Advanced oxide-isolated, ion-implanted Schottky TTL of 3-STATE logic elements configured as octal bus trans- process ceivers. These circuits are designed for use in memory, � Non-inverting logic output microprocessor systems and in asynchronous bidirectional � Glitch free bus during power up and down data buses. Two way communication between buses is � 3-STATE outputs independently controlled on A and B controlled by the (DIR) input. Data transmits either from the buses A bus to the B bus or from the B bus to the A bus. Both the driver and receiver outputs can be disabled via the (G) � Low output impedance to drive terminated transmission lines to 133Ω enable input which causes outputs to enter the high imped- ance mode so that the buses are effectively isolated. � Switching response specified into 500Ω/50 pF � Specified to interface with CMOS at V = V − 2V OH CC � PNP inputs to reduce input loading � Switching specifications guaranteed over full tempera- ture and V range CC Ordering Code: Order Number Package Number Package Description DM74ALS245AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74ALS245ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74ALS245AMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide DM74ALS245AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Control Inputs Operation G DIR L L B Data to A Bus L H A Data to B Bus H X Hi-Z H = HIGH Logic Level L = LOW Logic Level X = Either HIGH or LOW Logic Level © 2000 DS006213
