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74ALS09
Quad 2-Input AND Gate with Open Collector Outputs
DM74ALS09 Quad 2-Input AND Gate with Open Collector Outputs September 1986 Revised February 2000 DM74ALS09 Quad 2-Input AND Gate with Open Collector Outputs General Description Features This device contains four independent gates, each of which � Switching specifications at 50 pF performs the logic AND function. The open-collector out- � Switching specifications guaranteed over full tempera- puts require external pull-up resistors for proper logical ture and V range CC operation. � Advanced oxide-isolated, ion-implanted Schottky TTL Pull-Up Resistor Equations process � Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart � Improved AC performance over Schottky and low power Schottky counterparts Where: N (I ) = total maximum output HIGH current 1 OH for all outputs tied to pull-up resistor N (I ) = total maximum input HIGH current 2 IH for all inputs tied to pull-up resistor N (I ) = total maximum input LOW current for 3 IL all inputs tied to pull-up resistor Ordering Code: Order Number Package Number Package Description DM74ALS09M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS09N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y = AB Inputs Output AB Y LL L LH L HL L HH H H = HIGH Logic Level L = LOW Logic Level © 2000 DS006179
