74AHCT594DB Fast Delivery |IC PHOENIX CO.,LIMITED

74AHCT594DB ,8-bit shift register with output registerApplicationsn Serial-to parallel data conversionn Remote control holding register74AHC594; 74AHCT59 ..
74AHCT595PW ,8-bit serial-in/serial-out or parallel-out shift register with output latches; 3-stateINTEGRATED CIRCUITSDATA SHEET74AHC595; 74AHCT5958-bit serial-in/serial or parallel-outshift registe ..
74AHCT74 ,Dual D-type flip-flop with set and reset; positive-edge triggerPin configuration. Fig.2
74AHCT74D ,Dual D-type flip-flop with set and reset; positive-edge triggerPin configuration. Fig.2
74AHCT74PW ,Dual D-type flip-flop with set and reset; positive-edge triggerFeaturesn Balanced propagation delaysn All inputs have Schmitt-trigger actionsn Inputs accept volta ..
74AHCT86D ,Quad 2-input EXCLUSIVE-OR gateFeatures■ Balanced propagation delays■ All inputs have a Schmitt-trigger action■ Inputs accepts vol ..
74HC4024DB ,74HC4024; 7-stage binary ripple counter74HC40247-stage binary ripple counterRev. 03 — 12 November 2004 Product data sheet1.
74HC4024N ,74HC4024; 7-stage binary ripple counterGeneral descriptionThe 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the ..
74HC4024PW ,7-stage binary ripple counterGeneral descriptionThe 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the ..
74HC4040D ,12-stage binary ripple counterLogic diagram6. Pinning information6.1 Pinning terminal 1index areaQ5 2 15 Q10Q4 3 14 Q9Q11 1 16 VC ..
74HC4040N ,74HC/HCT4040; 12-stage binary ripple counterFEATURES (Q to Q ). The counter advances on the HIGH-to-LOW0 11transition of CP.• Output capability ..
74HC4040PW ,74HC/HCT4040; 12-stage binary ripple counterINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..

74AHCT594DB
8-bit shift register with output register
General descriptionThe 74AHC594; 74AHCT594isa high-speed Si-gate CMOS device andis pin compatible
with Low-Power Schottky TTL (LSTTL).Itis speciﬁedin compliance with JEDEC standard
No. 7-A.
The 74AHC594; 74AHCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register
that feedsan 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct
overriding clears (SHR and STR) are provided on both the shift and storage registers. serial output (Q7S) is provided for cascading purposes.
Both the shift and storage register clocks are positive-edge triggered.If the user wishesto
connect both clocks together, the shift register will alwaysbe one count pulse aheadof the
storage register. Features Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Wide supply voltage range from 2.0 Vto 5.5V 8-bit serial-in, parallel-out shift register with storage Independent direct overriding clears on shift and storage registers Independent clocks for shift and storage registers Latch-up performance exceeds 100 mA per JESD78 Class II Input levels: For 74AHC594: CMOS level For 74AHCT594: TTL level ESD protection: HBM EIA/JESD22-A114E exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V CDM EIA/JESD22-C101C exceeds 1000V Multiple package options Speciﬁed from −40 °C to +85 °C and from −40 °C to +125°C Applications Serial-to parallel data conversion Remote control holding register
74AHC594; 74AHCT594
8-bit shift register with output register
Rev. 02 — 9 June 2008 Product data sheet
NXP Semiconductors 74AHC594; 74AHCT594
8-bit shift register with output register Ordering information Functional diagram
Table 1. Ordering information
74AHC594
74AHC594D −40 °C to +125°C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74AHC594DB −40 °C to +125°C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74AHC594PW −40 °C to +125°C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74AHC594BQ −40 °C to +125°C DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad ﬂat package; no leads; 16 terminals;
body 2.5× 3.5× 0.85 mm
SOT763-1
74AHCT594
74AHCT594D −40 °C to +125°C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74AHCT594DB −40 °C to +125°C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74AHCT594PW −40 °C to +125°C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74AHCT594BQ −40 °C to +125°C DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad ﬂat package; no leads; 16 terminals;
body 2.5× 3.5× 0.85 mm
SOT763-1
NXP Semiconductors 74AHC594; 74AHCT594
8-bit shift register with output register
NXP Semiconductors 74AHC594; 74AHCT594
8-bit shift register with output register Pinning information
6.1 Pinning
NXP Semiconductors 74AHC594; 74AHCT594
8-bit shift register with output register
6.2 Pin description Functional description
[1]H= HIGH voltage state;= LOW voltage state;= LOW to HIGH transition;= don’t care;= no change;
Table 2. Pin description 1 parallel data output 2 parallel data output 3 parallel data output 4 parallel data output 5 parallel data output 6 parallel data output 7 parallel data output
GND 8 ground (0V)
Q7S 9 serial data output
SHR 10 shift register reset input (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input
STR 13 storage register reset input (active LOW) 14 serial data input 15 parallel data output
VCC 16 supply voltage
Table 3. Function table[1] X L X X L NC a LOW-state on SHR only affects the shift register X X L X NC L a LOW-state on STR only affects the storage register ↑ L H X L L empty shift register loaded into storage register X H X H Q6S NC logic HIGH level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S). ↑ H H X NC QnS contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages H H X Q6S QnS contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
NXP Semiconductors 74AHC594; 74AHCT594
8-bit shift register with output register Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For (T)SSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V [1] −20 - mA
IOK output clamping current VO < −0.5 V orVO >VCC+ 0.5V [1] −20 +20 mA output current VO = −0.5 V to (VCC+ 0.5V) −25 +25 mA
ICC supply current - +75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125°C [2]- 500 mW
NXP Semiconductors 74AHC594; 74AHCT594
8-bit shift register with output register Recommended operating conditions
10. Static characteristics
Table 5. Operating conditions
74AHC594
VCC supply voltage 2.0 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V
VCC = 4.5 V to 5.5 V - - 20 ns/V
74AHCT594
VCC supply voltage 4.5 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 4.5 V to 5.5 V - - 20 ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
74AHC594
VIH HIGH-level
input voltage
VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage
VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage = VIH or VIL= −50 μA; VCC= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V= −50 μA; VCC= 3.0 V 2.9 3.0 - 2.9 - 2.9 - V= −50 μA; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V= −4.0 mA; VCC= 3.0 V 2.58 - - 2.48 - 2.40 - V= −8.0 mA; VCC= 4.5 V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL = 50 μA; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 3.0 V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V = 4 mA; VCC= 3.0 V - - 0.36 - 0.44 - 0.55 V = 8 mA; VCC= 4.5 V - - 0.36 - 0.44 - 0.55 V
NXP Semiconductors 74AHC594; 74AHCT594
8-bit shift register with output register
11. Dynamic characteristics input leakage
current= 5.5Vor GND;
VCC =0Vto5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5V - 4.0 - 40 - 80 μA input
capacitance =VCCor GND - 3 10 - 10 - 10 pF
74AHCT594
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage = VIH or VIL= −50 μA; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V= −8.0 mA; VCC= 4.5 V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL = 50 μA; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V = 8 mA; VCC= 4.5 V - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5Vor GND;
VCC =0Vto5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5V - 4.0 - 40 - 80 μA
ΔICC additional
supply current
per input pin; =VCC− 2.1 V; other pins VCC or GND; IO= 0 A;
VCC= 4.5Vto 5.5V - 1.35 - 1.5 - 1.5 mA input
capacitance =VCCor GND - 3 10 - 10 - 10 pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 15.
74AHC594
tPLH LOW to HIGH
propagation
delay
SHCP to Q7S; see Figure9
VCC= 3.0Vto 3.6V=15pF - 5.2 8.5 2.2 9.7 2.2 10.6 ns=50pF - 7.4 11.5 3.0 13.2 3.0 14.3 ns
VCC= 4.5Vto 5.5V=15pF - 3.8 6.3 1.7 7.2 1.7 7.8 ns=50pF - 4.8 8.0 2.4 9.1 2.4 10.0 ns
NXP Semiconductors 74AHC594; 74AHCT594
8-bit shift register with output register
STCP to Qn; see Figure10
VCC= 3.0Vto 3.6V=15pF - 5.1 8.3 2.3 9.5 2.3 10.6 ns=50pF - 7.3 11.9 3.3 13.6 3.3 14.7 ns
VCC= 4.5Vto 5.5V=15pF - 3.5 5.7 1.8 6.5 1.8 7.1 ns=50pF - 4.8 7.8 2.6 9.0 2.6 9.8 ns
tPHL HIGH to LOW
propagation
delay
SHCP to Q7S; see Figure9
VCC= 3.0Vto 3.6V=15pF - 5.5 8.9 2.3 10.2 2.3 11.0 ns=50pF - 7.4 12.1 3.0 13.9 3.0 15.1 ns
VCC= 4.5Vto 5.5V=15pF - 4.1 6.7 1.9 7.6 1.9 8.2 ns=50pF - 5.4 8.8 2.5 10.1 2.5 11.0 ns
STCP to Qn; see Figure10
VCC= 3.0Vto 3.6V=15pF - 5.5 9.1 2.4 10.4 2.4 11.3 ns=50pF - 7.3 12.0 3.2 13.8 3.2 15.0 ns
VCC= 4.5Vto 5.5V=15pF - 3.7 6.0 1.9 6.9 1.9 7.5 ns=50pF - 5.2 8.5 2.6 9.7 2.6 10.5 ns
SHRto Q7S; see Figure13
VCC= 3.0Vto 3.6V=15pF - 5.7 9.5 2.3 10.8 2.3 11.7 ns=50pF - 7.5 12.2 3.6 14.0 3.6 15.2 ns
VCC= 4.5Vto 5.5V=15pF - 4.1 6.7 2.0 7.6 2.0 8.2 ns=50pF - 5.4 8.8 2.8 10.1 2.8 11.0 ns
STRto Qn; see Figure14
VCC= 3.0Vto 3.6V=15pF - 5.8 9.6 2.8 11.0 2.8 12.0 ns=50pF - 7.7 12.5 3.8 14.4 3.8 15.6 ns
VCC= 4.5Vto 5.5V=15pF - 4.1 7.2 2.2 8.2 2.2 8.9 ns=50pF - 5.4 9.4 3.0 10.7 3.0 11.6 ns
fmax maximum
frequency
SHCP or STCP;
see Figure9 and10
VCC = 3.0 V to 3.6 V 80 125 - 70 - 65 - MHz
VCC = 4.5 V to 5.5 V 90 170 - 80 - 70 - MHz
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 15.
NXP Semiconductors 74AHC594; 74AHCT594
8-bit shift register with output register pulse width SHCP and STCP HIGH or
LOW; see Figure 9 and10
VCC = 3.0 V to 3.6 V 6.0 - - 6.5 - 7.0 - ns
VCC = 4.5 V to 5.5 V 5.5 - - 6.0 - 6.5 - ns
SHR and STR HIGH or LOW;
see Figure 13 and14
VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.5 - ns
VCC = 4.5 V to 5.5 V 5.0 - - 5.2 - 5.7 - ns
tsu set-up time DSto SHCP; see Figure11
VCC = 3.0 V to 3.6 V 3.5 - - 3.5 - 4.0 - ns
VCC = 4.5 V to 5.5 V 3.0 - - 3.0 - 3.5 - ns
SHR to STCP; see Figure12
VCC = 3.0 V to 3.6 V 8.0 - - 9.0 - 9.5 - ns
VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.5 - ns
SHCP to STCP; see Figure10
VCC = 3.0 V to 3.6 V 8.0 - - 8.5 - 9.0 - ns
VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.5 - ns hold time DS to SHCP; see Figure11
VCC = 3.0 V to 3.6 V 1.5 - - 1.5 - 2.0 - ns
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.5 - ns
trec recovery time SHR to SHCP; see Figure13
VCC = 3.0 V to 3.6 V 4.2 - - 4.8 - 5.3 - ns
VCC = 4.5 V to 5.5 V 2.9 - - 3.3 - 3.8 - ns
STR to STCP; see Figure14
VCC = 3.0 V to 3.6 V 4.6 - - 5.3 - 5.8 - ns
VCC = 4.5 V to 5.5 V 3.2 - - 3.7 - 4.3 - ns
CPD power
dissipation
capacitance=1 MHz; VI = GND to VCC [2] -55 - - - - - pF
74AHCT594; VCC = 4.5 V to 5.5 V
tPLH LOW to HIGH
propagation
delay
SHCP to Q7S; see Figure9=15pF - 3.8 6.3 1.7 7.2 1.7 7.8 ns=50pF - 4.8 8.0 2.2 9.1 2.2 9.9 ns
STCP to Qn; see Figure10=15pF - 3.5 5.7 1.8 6.5 1.8 7.1 ns=50pF - 4.6 7.7 2.6 8.8 2.6 9.6 ns
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 15.
NXP Semiconductors 74AHC594; 74AHCT594
8-bit shift register with output register
[1] Typical values are measured at nominal supply voltage (VCC=3.3 V and VCC=5.0V).
[2] CPDis used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs.
tPHL HIGH to LOW
propagation
delay
SHCP to Q7S; see Figure9=15pF - 4.1 6.7 1.8 7.6 1.8 8.3 ns=50pF - 5.4 8.8 2.4 10.1 2.4 11.0 ns
STCP to Qn; see Figure10=15pF - 3.7 6.1 1.9 6.9 1.9 7.2 ns=50pF - 5.2 8.5 2.6 9.7 2.6 10.5 ns
SHRto Q7S; see Figure13=15pF - 4.3 7.0 2.4 8.0 2.4 8.7 ns=50pF - 5.4 8.8 2.7 10.1 2.7 11.0 ns
STRto Qn; see Figure14=15pF - 4.5 7.4 2.3 8.4 2.3 9.2 ns=50pF - 5.7 9.4 3.1 10.7 3.1 11.7 ns
fmax maximum
frequency
SHCP or STCP;
see Figure9 and10 160 - 80 - 70 - MHz pulse width SHCP and STCP HIGH or
LOW; see Figure 9 and10
5.5 - - 6.0 - 6.5 - ns
SHR and STR HIGH or LOW;
see Figure 13 and14
5.2 - - 5.5 - 6.0 - ns
tsu set-up time DS to SHCP; see Figure11 3.0 - - 3.0 - 3.5 - ns
SHR to STCP; see Figure12 5.0 - - 5.0 - 5.5 - ns
SHCP to STCP; see Figure10 5.0 - - 5.0 - 5.5 - ns hold time DSto SHCP; see Figure11 2.0 - - 2.0 - 2.5 - ns
trec recovery time SHRto SHCP; see Figure13 2.9 - - 3.3 - 3.8 - ns
STRto STCP; see Figure14 3.4 - - 3.8 - 4.3 - ns
CPD power
dissipation
capacitance=1 MHz; VI = GND to VCC [2] -55 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 15.

Partno	Mfg	Dc	Qty	Available	Descript
74AHCT594DB	NXP	N/a	10000	avai	8-bit shift register with output register