74AHCT374D-74AHCT374PW Fast Delivery |IC PHOENIX CO.,LIMITED

74AHCT374PW ,Octal D-type flip-flop; positive edge-trigger; 3-stateapplications. A clock input(CP) and an output enable input (OE) are common to all ﬂip-ﬂops.The eigh ..
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74AHCT374D-74AHCT374PW
Octal D-type flip-flop; positive edge-trigger; 3-state
General descriptionThe 74AHC374; 74AHCT374isa high-speed Si-gate CMOS device andis pin compatible
with Low-power Schottky TTL (LSTTL).Itis speciﬁedin compliance with JEDEC standard
No. 7-A.
The 74AHC374; 74AHCT374 comprises eight D-type ﬂip-ﬂops featuring separate D-type
inputs for each ﬂip-ﬂop and 3-state outputs for bus oriented applications. A clock input
(CP) and an output enable input (OE) are common to all ﬂip-ﬂops.
The eight ﬂip-ﬂops will store the stateof their individualD inputs that meet the set-up and
hold times requirements for the LOW-to-HIGH CP transition.
When OEis LOW the contentof the eight ﬂip-ﬂopsis availableat the outputs. When OEis
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the ﬂip-ﬂops. Features Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Common 3-state output enable input Input levels: For 74AHC374: CMOS level For 74AHCT374: TTL level ESD protection: HBM EIA/JESD22-A114E exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V CDM EIA/JESD22-C101C exceeds 1000V Multiple package options Speciﬁed from −40 °C to +85 °C and from −40 °C to +125°C
74AHC374; 74AHCT374
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state
Rev. 03 — 12 June 2008 Product data sheet
NXP Semiconductors 74AHC374; 74AHCT374
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state Ordering information Functional diagram
Table 1. Ordering information
74AHC374
74AHC374D −40 °C to +125°C SO20 plastic small outline package; 20 leads; body
width 7.5 mm
SOT163-1
74AHC374PW −40 °C to +125°C TSSOP20 plastic thin shrink small outline package;20 leads;
body width 4.4 mm
SOT360-1
74AHCT374
74AHCT374D −40 °C to +125°C SO20 plastic small outline package; 20 leads; body
width 7.5 mm
SOT163-1
74AHCT374PW −40 °C to +125°C TSSOP20 plastic thin shrink small outline package;20 leads;
body width 4.4 mm
SOT360-1
NXP Semiconductors 74AHC374; 74AHCT374
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state
NXP Semiconductors 74AHC374; 74AHCT374
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 3-state output enable input (active LOW) 2 3-state ﬂip-ﬂop output 3 data input 4 data input 5 3-state ﬂip-ﬂop output 6 3-state ﬂip-ﬂop output 7 data input 8 data input 9 3-state ﬂip-ﬂop output
GND 10 ground (0V) 11 clock input (LOW-to-HIGH, edge triggered) 12 3-state ﬂip-ﬂop output 13 data input 14 data input 15 3-state ﬂip-ﬂop output 16 3-state ﬂip-ﬂop output 17 data input 18 data input 19 3-state ﬂip-ﬂop output
VCC 20 supply voltage
NXP Semiconductors 74AHC374; 74AHCT374
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state Functional description
[1]H= HIGH voltage level;
h = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition;= LOW voltage level;= LOW voltage level one setup time prior to the LOW-to-HIGH CP transition;
X = don’t care;
↑ = LOW-to-HIGH CP transition;= high-impedance OFF-state. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
Table 3. Function table[1]
Load and read register L ↑ lL L ↑ hH H
Load register and disable outputs H ↑ lL Z ↑ hH Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5V [1] −20 - mA
IOK output clamping current VO < −0.5 V or VO > VCC + 0.5V [1] −20 +20 mA output current VO = −0.5 V to (VCC + 0.5V) −25 +25 mA
ICC supply current - +75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb= −40°Cto +125°C [2]- 500 mW
NXP Semiconductors 74AHC374; 74AHCT374
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state Recommended operating conditions Static characteristics
Table 5. Operating conditions
74AHC374
VCC supply voltage 2.0 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC= 3.0Vto 3.6V - - 100 ns/V
VCC= 4.5Vto 5.5V - - 20 ns/V
74AHCT374
VCC supply voltage 4.5 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC= 4.5Vto 5.5V - - 20 ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
74AHC374
VIH HIGH-level
input voltage
VCC= 2.0V 1.5 - - 1.5 - 1.5 - V
VCC= 3.0V 2.1 - - 2.1 - 2.1 - V
VCC= 5.5V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage
VCC= 2.0V - - 0.5 - 0.5 - 0.5 V
VCC= 3.0V - - 0.9 - 0.9 - 0.9 V
VCC= 5.5V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage =VIHorVIL= −50 μA; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= −50 μA; VCC= 3.0V 2.9 3.0 - 2.9 - 2.9 - V= −50 μA; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= −4.0 mA; VCC= 3.0V 2.58 - - 2.48 - 2.40 - V= −8.0 mA; VCC= 4.5V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage =VIHorVIL =50 μA; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =50 μA; VCC= 3.0V - 0 0.1 - 0.1 - 0.1 V =50 μA; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V= 4.0 mA; VCC= 3.0V - - 0.36 - 0.44 - 0.55 V= 8.0 mA; VCC= 4.5V - - 0.36 - 0.44 - 0.55 V
NXP Semiconductors 74AHC374; 74AHCT374
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state input leakage
current= 5.5Vor GND;
VCC=0Vto 5.5V - 0.1 - 1.0 - 2.0 μA
IOZ OFF-state
output current =VIHor VIL; =VCCor GND;
VCC= 5.5V ±0.25 - ±2.5 - ±10.0 μA
ICC supply current VI =VCCor GND; IO =0A;
VCC= 5.5V - 4.0 - 40 - 80 μA input
capacitance =VCCor GND - 3 10 - 10 - 10 pF output
capacitance 4 - - --- pF
74AHCT374
VIH HIGH-level
input voltage
VCC = 4.5Vto 5.5V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5Vto 5.5V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC= 4.5V= −50μA 4.4 4.5 - 4.4 - 4.4 - V= −8.0 mA 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage =VIHor VIL; VCC= 4.5V =50μA - 0 0.1 - 0.1 - 0.1 V= 8.0 mA - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5Vor GND;
VCC=0Vto 5.5V - 0.1 - 1.0 - 2.0 μA
IOZ OFF-state
output current =VIHor VIL; =VCCor GND per input
pin; other inputs at
VCCor GND; IO =0A;
VCC= 5.5V ±0.25 - ±2.5 - ±10.0 μA
ICC supply current VI =VCCor GND; IO =0A;
VCC= 5.5V - 4.0 - 40 - 80 μA
ΔICC additional
supply current
per input pin; =VCC− 2.1 V; other pins
at VCCor GND; IO =0A;
VCC= 4.5Vto 5.5V - 1.35 - 1.5 - 1.5 mA input
capacitance =VCCor GND - 3 10 - 10 - 10 pF output
capacitance 4 - - --- pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
NXP Semiconductors 74AHC374; 74AHCT374
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure9.
74AHC374
tpd propagation
delayto Qn; see Figure 6 and
Figure8
[2]
VCC= 3.0Vto 3.6V=15pF - 6.4 12.7 1.0 15.0 1.0 16.0 ns=50pF - 8.4 16.2 1.0 18.5 1.0 20.5 ns
VCC= 4.5Vto 5.5V=15pF - 4.4 8.1 1.0 9.5 1.0 10.0 ns=50pF - 5.7 10.1 1.0 11.5 1.0 12.5 ns
ten enable time OEto Qn; see Figure7 [3]
VCC= 3.0Vto 3.6V=15pF - 5.5 11.0 1.0 13.0 1.0 14.0 ns=50pF - 7.3 14.5 1.0 16.5 1.0 18.0 ns
VCC= 4.5Vto 5.5V=15pF - 3.9 7.6 1.0 9.0 1.0 9.5 ns=50pF - 5.2 9.6 1.0 11.0 1.0 12.0 ns
tdis disable time OEto Qn; see Figure7 [4]
VCC= 3.0Vto 3.6V=15pF - 5.6 10.5 1.0 12.5 1.0 13.0 ns=50pF - 9.4 14.0 1.0 16.0 1.0 17.5 ns
VCC= 4.5Vto 5.5V=15pF - 4.2 6.8 1.0 8.0 1.0 8.5 ns=50pF - 6.4 8.8 1.0 10.0 1.0 11.0 ns
fmax maximum
frequency
see Figure6
VCC= 3.0Vto 3.6V=15pF 80 130 - 70 - 70 - MHz=50pF 55 85 - 50 - 50 - MHz
VCC= 4.5Vto 5.5V=15pF 130 185 - 110 - 110 - MHz=50pF 85 120 - 75 - 75 - MHz pulse width CP HIGHor LOW;
see Figure6
VCC= 3.0Vto 3.6V 5.0 - - 5.5 - 5.5 - ns
VCC= 4.5Vto 5.5V 5.0 - - 5.0 - 5.0 - ns
tsu set-up time Dn to CP; see Figure8
VCC= 3.0Vto 3.6V 4.5 - - 4.0 - 4.0 - ns
VCC= 4.5Vto 5.5V 3.0 - - 3.0 - 3.0 - ns
NXP Semiconductors 74AHC374; 74AHCT374
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state
[1] Typical values are measured at nominal supply voltage (VCC=3.3 V and VCC=5.0V).
[2] tpd is the same as tPLH and tPHL.
[3] ten is the same as tPZH and tPZL.
[4] tdis is the same as tPHZ and tPLZ.
[5] CPDis used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs. hold time Dn to CP; see Figure8
VCC= 3.0Vto 3.6V 2.0 - - 2.0 - 2.0 - ns
VCC= 4.5Vto 5.5V 2.0 - - 2.0 - 2.0 - ns
CPD power
dissipation
capacitance=1 MHz; VI= GNDto VCC [5] -10 - - - - - pF
74AHCT374; VCC= 4.5Vto 5.5V
tpd propagation
delayto Qn; see Figure 6 and
Figure8
[2]=15pF - 4.3 9.4 1.0 10.5 1.0 12.0 ns=50pF - 5.6 10.4 1.0 11.5 1.0 13.0 ns
ten enable time OEto Qn; see Figure7 [3]=15pF - 3.5 10.2 1.0 11.5 1.0 13.0 ns=50pF - 4.8 11.2 1.0 12.5 1.0 14.0 ns
tdis disable time OEto Qn; see Figure7 [4]=15pF - 3.6 10.2 1.0 11.0 1.0 13.0 ns=50pF - 5.7 11.2 1.0 12.0 1.0 14.0 ns
fmax maximum
frequency
see Figure6=15pF 90 140 - 80 - 80 - MHz=50pF 85 130 - 75 - 75 - MHz pulse width CP HIGHor LOW;
see Figure6
6.5 - - 6.5 - 6.5 - ns
tsu set-up time Dn to CP; see Figure8 2.5 - - 2.5 - 2.5 - ns hold time Dn to CP; see Figure8 2.5 - - 2.5 - 2.5 - ns
CPD power
dissipation
capacitance=1 MHz; VI= GNDto VCC [5] -12 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure9.

Partno	Mfg	Dc	Qty	Available	Descript
74AHCT374D	NXP	N/a	2000	avai	Octal D-type flip-flop; positive edge-trigger; 3-state
74AHCT374PW	NXP	N/a	7500	avai	Octal D-type flip-flop; positive edge-trigger; 3-state
74AHCT374PW		N/a	12500	avai	Octal D-type flip-flop; positive edge-trigger; 3-state