74AHCT74D ,Dual D-type flip-flop with set and reset; positive-edge triggerPin configuration. Fig.2
74AHCT74PW ,Dual D-type flip-flop with set and reset; positive-edge triggerFeaturesn Balanced propagation delaysn All inputs have Schmitt-trigger actionsn Inputs accept volta ..
74AHCT86D ,Quad 2-input EXCLUSIVE-OR gateFeatures■ Balanced propagation delays■ All inputs have a Schmitt-trigger action■ Inputs accepts vol ..
74AHCT86D ,Quad 2-input EXCLUSIVE-OR gateGeneral descriptionThe 74AHC86; 74AHCT86 are high-speed Si-gate CMOS devices and are pin compatible ..
74AHCT86PW ,Quad 2-input EXCLUSIVE-OR gateFEATURES QUICK REFERENCE DATAGround = 0 V; T =25 °C; t =t ≤ 3.0 ns.amb r f• ESD protection:HBM EIA/ ..
74AHCT86PW ,Quad 2-input EXCLUSIVE-OR gate74AHC86; 74AHCT86Quad 2-input EXCLUSIVE-OR gateRev. 02 — 15 November 2007 Product data sheet1.
74HC4024N ,74HC4024; 7-stage binary ripple counterGeneral descriptionThe 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the ..
74HC4024PW ,7-stage binary ripple counterGeneral descriptionThe 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the ..
74HC4040D ,12-stage binary ripple counterLogic diagram6. Pinning information6.1 Pinning terminal 1index areaQ5 2 15 Q10Q4 3 14 Q9Q11 1 16 VC ..
74HC4040N ,74HC/HCT4040; 12-stage binary ripple counterFEATURES (Q to Q ). The counter advances on the HIGH-to-LOW0 11transition of CP.• Output capability ..
74HC4040PW ,74HC/HCT4040; 12-stage binary ripple counterINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC4046 ,Phase-locked-loop with VCO
74AHC74PW -74AHCT74-74AHCT74D
Dual D-type flip-flop with set and reset; positive-edge trigger
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
FEATURES ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000V EIA/JESD22-A115-A
exceeds 200V Balanced propagation delays Inputs acceptsvoltageshigher than
VCC For AHC only:
operates with CMOS input levels For AHCT only:
operates with TTL input levels Output capability: standard ICC category: flip-flops Specified from
−40to +85 and +125 °C.
DESCRIPTIONThe 74AHC/AHCT74 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.
The 74AHC/AHCT74 dual
positive-edge triggered, D-type
flip-flops with individual data (D)
inputs, clock (CP) inputs,set (SD) and
reset (RD) inputs; also
complementary Q andQ outputs.
The set and reset are asynchronous
active LOW inputs and operate
independently of the clock input.
Information on the data input is
transferred to the Q output on the
LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable
one set-up time prior to the
LOW-to-HIGH clock transition for
predictable operation.
Schmitt-trigger action in the clock
input makes the circuit highly tolerant
to slower clock rise and fall times.
QUICK REFERENCE DATAGND=0 V; Tamb =25 °C; tr =tf≤ 3.0 ns.
Notes CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi+∑ (CL× VCC2×fo) where:= input frequency in MHz; fo= output frequency in MHz; (CL× VCC2×fo)= sum of outputs;= output load capacitance in pF;
VCC= supply voltage in Volts. The condition is VI= GNDto VCC.
FUNCTION TABLES
Table 1 See note1
Table 2 See note1
Note to Tables1 and2 H= HIGH voltage level;= LOW voltage level;= don’t care;= LOW-to-HIGH CP transition;
Qn+1= state after the next LOW-to-HIGH CP transition.
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
ORDERING INFORMATION
PINNING
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground=0V).
Notes The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
DC CHARACTERISTICS
74AHC familyOver recommended operating conditions; voltage are referenced to GND (ground=0 V).
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
74AHCT familyOver recommended operating conditions; voltage are referenced to GND (ground=0 V).
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
AC CHARACTERISTICS
Type 74AHC74GND=0 V; tr =tf≤ 3.0 ns.
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
Notes Typical values at VCC= 3.3V. Typical values at VCC= 5.0V.
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
Type 74AHCT74GND=0 V; tr =tf≤ 3.0 ns.
Note Typical values at VCC= 5.0V.
