74AHC74D-74AHCT74PW Fast Delivery |IC PHOENIX CO.,LIMITED

74AHC74D ,Dual D-type flip-flop with set and reset; positive-edge triggerGeneral descriptionThe 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatiblew ..
74AHC74PW ,Dual D-type flip-flop with set and reset; positive-edge triggerINTEGRATED CIRCUITSDATA SHEET74AHC74; 74AHCT74Dual D-type flip-flop with set andreset; positive-edg ..
74AHC86D ,Quad 2-input EXCLUSIVE-OR gateFeatures■ Balanced propagation delays■ All inputs have a Schmitt-trigger action■ Inputs accepts vol ..
74AHC86D ,Quad 2-input EXCLUSIVE-OR gateINTEGRATED CIRCUITSDATA SHEET74AHC86; 74AHCT86Quad 2-input EXCLUSIVE-OR gateProduct speciﬁcation 19 ..
74AHC86PW ,Quad 2-input EXCLUSIVE-OR gateLogic diagram (one gate) Fig 3. IEC logic symbol74AHC_AHCT86_2 NXP B.V. 2007. All rights reserved. ..
74AHCT00PW ,Quad 2-input NAND gate
74HC374 ,3-stateMAXIMUM RATINGSÎÎ Symbol Parameter Value UnitThis device contains protectioncircuitry to guard agai ..
74HC374D ,74HC/HCT374; Octal D-type flip-flop; positive edge-trigger; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC374DB ,Octal D-type flip-flop; positive edge-trigger; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC374N ,74HC/HCT374; Octal D-type flip-flop; positive edge-trigger; 3-stateGENERAL DESCRIPTIONThe “374” is functionally identical to the “534”, but hasThe 74HC/HCT374 are hig ..
74HC374N.. ,74HC/HCT374; Octal D-type flip-flop; positive edge-trigger; 3-stateGENERAL DESCRIPTIONThe “374” is functionally identical to the “534”, but hasThe 74HC/HCT374 are hig ..
74HC374PW ,Octal D-type flip-flop; positive edge-trigger; 3-stateFEATURES The 74HC/HCT374 are octal D-type flip-flops featuringseparate D-type inputs for each flip- ..

74AHC74D-74AHCT74PW
Dual D-type flip-flop with set and reset; positive-edge trigger
General descriptionThe 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL).Itis speciﬁedin compliance with JEDEC standard
No. 7-A.
The 74AHC74; 74AHCT74isa dual positive-edge triggered, D-type ﬂip-ﬂop with individual
data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has
complementary outputs (Q and Q).
The set and reset are asynchronous active LOW inputs that operate independent of the
clock input. Information on the data input is transferred to the Q output on the LOW to
HIGH transitionof the clock pulse. The data inputs mustbe stable one set-up time priorto
the LOW to HIGH clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times. Features Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Input levels: For 74AHC74: CMOS level For 74AHCT74: TTL level ESD protection: HBM EIA/JESD22-A114E exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V CDM EIA/JESD22-C101C exceeds 1000V Multiple package options Speciﬁed from −40 °C to +85 °C and from −40 °C to +125°C
74AHC74; 74AHCT74
Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger
Rev. 05 — 9 June 2008 Product data sheet
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger Ordering information Functional diagram
Table 1. Ordering information
74AHC74
74AHC74D −40 °C to +125°C SO14 plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74AHC74PW −40 °C to +125°C TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
SOT402-1
74AHC74BQ −40 °C to +125°C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad ﬂat package; no leads; 14 terminals;
body 2.5×3× 0.85 mm
SOT762-1
74AHCT74
74AHCT74D −40 °C to +125°C SO14 plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74AHCT74PW −40 °C to +125°C TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
SOT402-1
74AHCT74BQ −40 °C to +125°C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad ﬂat package; no leads; 14 terminals;
body 2.5×3× 0.85 mm
SOT762-1
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
1RD 1 asynchronous reset direct input (active LOW) 2 data input
1CP 3 clock input (LOW to HIGH, edge-triggered)
1SD 4 asynchronous set direct input (active LOW) 5 true ﬂip-ﬂop output 6 complement ﬂip-ﬂop output
GND 7 ground (0V) 8 complement ﬂip-ﬂop output 9 true ﬂip-ﬂop output
2SD 10 asynchronous set direct input (active LOW)
2CP 11 clock input (LOW to HIGH, edge-triggered) 12 data input
2RD 13 asynchronous reset direct input (active LOW)
VCC 14 supply voltage
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger Functional description
[1]H= HIGH voltage level;= LOW voltage level;= LOW to HIGH transition;
Qn+1= state after the next LOW to HIGH CP transition;= don’t care. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.
Table 3. Function table[1] X X H L LH X X L H HL
LLX X H H - - ↑ L- - L H ↑ H- - H L
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5V [1] −20 - mA
IOK output clamping current VO < −0.5 V or VO > VCC + 0.5V [1] −20 +20 mA output current VO = −0.5V to (VCC + 0.5V) −25 +25 mA
ICC supply current - +75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb= −40°Cto +125°C [2]- 500 mW
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger Recommended operating conditions Static characteristics
Table 5. Operating conditions
74AHC74
VCC supply voltage 2.0 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC= 3.0Vto 3.6V - - 100 ns/V
VCC= 4.5Vto 5.5V - - 20 ns/V
74AHCT74
VCC supply voltage 4.5 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC= 4.5Vto 5.5V - - 20 ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
74AHC74
VIH HIGH-level
input voltage
VCC= 2.0V 1.5 - - 1.5 - 1.5 - V
VCC= 3.0V 2.1 - - 2.1 - 2.1 - V
VCC= 5.5V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage
VCC= 2.0V - - 0.5 - 0.5 - 0.5 V
VCC= 3.0V - - 0.9 - 0.9 - 0.9 V
VCC= 5.5V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage =VIHorVIL= −50 μA; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= −50 μA; VCC= 3.0V 2.9 3.0 - 2.9 - 2.9 - V= −50 μA; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= −4.0 mA; VCC= 3.0V 2.58 - - 2.48 - 2.40 - V= −8.0 mA; VCC= 4.5V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage =VIHorVIL =50 μA; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =50 μA; VCC= 3.0V - 0 0.1 - 0.1 - 0.1 V =50 μA; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V= 4.0 mA; VCC= 3.0V - - 0.36 - 0.44 - 0.55 V= 8.0 mA; VCC= 4.5V - - 0.36 - 0.44 - 0.55 V
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger input leakage
current= 5.5Vor GND;
VCC=0Vto 5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply current VI =VCCor GND; IO =0A;
VCC= 5.5V - 2.0 - 20 - 40 μA input
capacitance =VCCor GND - 3 10 - 10 - 10 pF
74AHCT74
VIH HIGH-level
input voltage
VCC = 4.5Vto 5.5V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5Vto 5.5V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC= 4.5V= −50μA 4.4 4.5 - 4.4 - 4.4 - V= −8.0 mA 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage =VIHor VIL; VCC= 4.5V =50μA - 0 0.1 - 0.1 - 0.1 V= 8.0 mA - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5Vor GND;
VCC=0Vto 5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply current VI =VCCor GND; IO =0A;
VCC= 5.5V - 2.0 - 20 - 40 μA
ΔICC additional
supply current
per input pin; =VCC− 2.1 V; other pins
at VCCor GND; IO =0A;
VCC= 4.5Vto 5.5V - 1.35 - 1.5 - 1.5 mA input
capacitance =VCCor GND - 3 10 - 10 - 10 pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure9.
74AHC74
tpd propagation
delay
nCPto nQ, nQ; see Figure7 [2]
VCC= 3.0Vto 3.6V=15pF - 5.2 11.9 1.0 14.0 1.0 15.0 ns=50pF - 7.4 15.4 1.0 17.5 1.0 19.5 ns
VCC= 4.5Vto 5.5V=15pF - 3.7 7.3 1.0 8.5 1.0 9.5 ns=50pF - 5.2 9.3 1.0 10.5 1.0 12.0 ns
nSD, nRD to nQ, nQ;
see Figure8
VCC= 3.0Vto 3.6V=15pF - 5.4 12.3 1.0 14.5 1.0 15.5 ns=50pF - 7.7 15.8 1.0 18.0 1.0 20.0 ns
VCC= 4.5Vto 5.5V=15pF - 3.7 7.7 1.0 9.0 1.0 10.0 ns=50pF - 5.3 9.7 1.0 11.0 1.0 12.5 ns
fmax maximum
frequency
see Figure7
VCC= 3.0Vto 3.6V=15pF 80 125 - 45 - 45 - MHz=50pF 50 75 - 70 - 70 - MHz
VCC= 4.5Vto 5.5V=15pF 130 170 - 110 - 110 - MHz=50pF 90 115 - 75 - 75 - MHz pulse width CP HIGHor LOW;
nSD, nRD LOW;
see Figure7 and8
VCC= 3.0Vto 3.6V 6.0 - - 7.0 - 7.0 - ns
VCC= 4.5Vto 5.5V 5.0 - - 5.0 - 5.0 - ns
tsu set-up time nD to nCP; see Figure7
VCC= 3.0Vto 3.6V 6.0 - - 7.0 - 7.0 - ns
VCC= 4.5Vto 5.5V 5.0 - - 5.0 - 5.0 - ns hold time nD to nCP; see Figure7
VCC= 3.0Vto 3.6V 0.5 - - 0.5 - 0.5 - ns
VCC= 4.5Vto 5.5V 0.5 - - 0.5 - 0.5 - ns
trec recovery
time
nRD to nCP; see Figure8
VCC= 3.0Vto 3.6V 5.0 - - 5.0 - 5.0 - ns
VCC= 4.5Vto 5.5V 3.0 - - 3.0 - 3.0 - ns
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger
[1] Typical values are measured at nominal supply voltage (VCC=3.3 V and VCC=5.0V).
[2] tpd is the same as tPLH and tPHL.
[3] CPDis used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs.
CPD power
dissipation
capacitance=1 MHz; VI= GNDto VCC [3] -12- - - - - pF
74AHCT74; VCC= 4.5Vto 5.5V
tpd propagation
delay
nCPto nQ, nQ; see Figure7 [2]=15pF - 3.3 7.8 1.0 9.0 1.0 10.0 ns=50pF - 4.8 8.8 1.0 10.0 1.0 11.0 ns
nSD, nRD to nQ, nQ;
see Figure7=15pF - 3.7 10.4 1.0 12.0 1.0 13.0 ns=50pF - 5.3 11.4 1.0 13.0 1.0 14.5 ns
fmax maximum
frequency
see Figure7=15pF 100 160 - 80 - 80 - MHz=50pF 80 140 - 65 - 65 - MHz pulse width CP HIGHor LOW;
nSD, nRD LOW;
see Figure7 and8
5.0 - - 5.0 - 5.0 - ns
tsu set-up time nD to nCP; see Figure7 5.0 - - 5.0 - 5.0 - ns hold time nD to nCP; see Figure7 0- - 0 - 0 - ns
trec recovery
time
nRD to nCP; see Figure8 3.5 - - 3.5 - 3.5 - ns
CPD power
dissipation
capacitance=1 MHz; VI= GNDto VCC [3] -16- - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure9.

Partno	Mfg	Dc	Qty	Available	Descript
74AHC74D	NXP	N/a	13368	avai	Dual D-type flip-flop with set and reset; positive-edge trigger
74AHCT74PW		N/a	12500	avai	Dual D-type flip-flop with set and reset; positive-edge trigger