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74AHC595D ,8-bit serial-in/serial-out or parallel-out shift register with output latches; 3-stateGeneral descriptionThe 74AHC595; 74AHCT595 are high-speed Si-gate CMOS devices and are pin compatib ..
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74AHC595D
8-bit serial-in/serial-out or parallel-out shift register with output latches; 3-state
1. General description
The 74AHC595; 74AHCT595 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC595; 74AHCT595 are 8-stage serial shift registers with a storage register and
3-state outputs. The registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP).
The data in each register is transferred to the storage register on a positive-going
transition of the storage register clock input (STCP). If both clocks are connected together,
the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW.
2. Features and benefits Balanced propagation delays All inputs have Schmitt-trigger action Inputs accept voltages higher than VCC Input levels: The 74AHC595 operates with CMOS input levels The 74AHCT595 operates with TTL input levels ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V CDM JESD22-C101E exceeds 1000V Multiple package options Specified from 40 C to +85 C and from 40 C to +125C
3. Applications Serial-to-parallel data conversion Remote control holding register
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with
output latches
Rev. 5 — 4 July 2012 Product data sheet
NXP Semiconductors 74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
4. Ordering information
5. Functional diagram
Table 1. Ordering information
74AHC595
74AHC595D 40 C to +125 C SO16 plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
74AHC595PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74AHC595BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; terminals; body 2.5 3.5 0.85 mm
SOT763-1
74AHCT595
74AHCT595D 40 C to +125 C SO16 plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
74AHCT595PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74AHCT595BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; terminals; body 2.5 3.5 0.85 mm
SOT763-1
NXP Semiconductors 74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
NXP Semiconductors 74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin description 1 parallel data output 1 2 parallel data output 2 3 parallel data output 3 4 parallel data output 4 5 parallel data output 5 6 parallel data output 6 7 parallel data output 7
GND 8 ground (0 V)
Q7S 9 serial data output 10 master reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input 13 output enable input (active LOW) 14 serial data input 15 parallel data output 0
VCC 16 supply voltage
NXP Semiconductors 74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
7. Functional description
[1] H= HIGH voltage state;= LOW voltage state;= LOW-to-HIGH transition;= don’t care;= no change;= high-impedance OFF-state.
Table 3. Function table[1] X L L X L NC a LOW-level on MR only affects the shift registers  L L X L L empty shift register loaded into storage register X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).  L H X NC QnS contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages L H X Q6S QnS contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
NXP Semiconductors 74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For TSSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of Ptot derates linearly at 4.5 mW/K.
9. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage 0.5 +7.0 V input voltage 0.5 +7.0 V
IIK input clamping current VI< 0.5V [1] 20 - mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V [1] 20 +20 mA output current VO= 0.5 V to (VCC +0.5V) 25 +25 mA
ICC supply current - +75 mA
IGND ground current 75 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125C [2]- 500 mW
Table 5. Operating conditions
74AHC595
VCC supply voltage 2.0 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and fall rate VCC= 3.0 V to 3.6V - - 100 ns/V
VCC= 4.5 V to 5.5V - - 20 ns/V
74AHCT595
VCC supply voltage 4.5 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and fall rate VCC= 4.5 V to 5.5V - - 20 ns/V
NXP Semiconductors 74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
10. Static characteristicsTable 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
74AHC595
VIH HIGH-level
input voltage
VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage
VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage = VIH or VIL = 50 A; VCC= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V = 50 A; VCC= 3.0 V 2.9 3.0 - 2.9 - 2.9 - V = 50 A; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V = 4.0 mA; VCC= 3.0 V 2.58 - - 2.48 - 2.40 - V = 8.0 mA; VCC= 4.5 V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL = 50 A; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V = 50 A; VCC= 3.0 V - 0 0.1 - 0.1 - 0.1 V = 50 A; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V = 4.0 mA; VCC= 3.0 V - - 0.36 - 0.44 - 0.55 V = 8.0 mA; VCC= 4.5 V - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5 Vor GND;
VCC =0Vto5.5V - 0.1 - 1.0 - 2.0 A
IOZ OFF-state
output current =VIHor VIL; =VCCor GND; VCC =5.5V 0.25 - 2.5 - 10 A
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC =5.5V 4.0 - 40 - 80 A input
capacitance 3 10 - 10 - 10 pF
74AHCT595
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage = VIH or VIL; VCC= 4.5 V = 50A 4.4 4.5 - 4.4 - 4.4 - V = 8.0 mA 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL; VCC= 4.5 V = 50A - 0 0.1 - 0.1 - 0.1 V = 8.0 mA - - 0.36 - 0.44 - 0.55 V
NXP Semiconductors 74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches input leakage
current= 5.5 Vor GND;
VCC =0Vto5.5V - 0.1 - 1.0 - 2.0 A
IOZ OFF-state
output current =VIHor VIL; =VCCor GND per input pin;
other inputs at VCCor GND; =0 A; VCC =5.5V 0.25 - 2.5 - 10 A
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC =5.5V 4.0 - 40 - 80 A
ICC additional
supply current
per input pin; VI =VCC 2.1V;
other inputsat VCC or GND; =0 A; VCC= 4.5Vto 5.5V - 1.35 - 1.5 - 1.5 mA input
capacitance 3 10 - 10 - 10 pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
11. Dynamic characteristicsTable 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
74AHC595
tpd propagation
delay
SHCPto Q7S; see Figure8 [2]
VCC = 3.0 V to 3.6 V=15pF - 5.7 13.0 1.0 15.0 1.0 16.5 ns=50pF - 7.7 16.5 1.0 18.5 1.0 20.1 ns
VCC = 4.5 V to 5.5 V=15pF - 4.0 8.2 1.0 9.4 1.0 10.5 ns=50pF - 5.4 10.0 1.0 11.4 1.0 12.5 ns
STCPto Qn; see Figure9 [2]
VCC = 3.0 V to 3.6 V=15pF - 5.9 11.9 1.0 13.5 1.0 15.0 ns=50pF - 7.7 15.4 1.0 17.0 1.0 18.5 ns
VCC = 4.5 V to 5.5 V=15pF - 4.2 7.4 1.0 8.5 1.0 9.5 ns=50pF - 5.5 9.0 1.0 10.5 1.0 11.5 nsto Q7S; see Figure11 [3]
VCC = 3.0 V to 3.6 V=15pF - 5.9 12.8 1.0 13.7 1.0 15.0 ns=50pF - 7.4 16.3 1.0 17.2 1.0 18.7 ns
VCC = 4.5 V to 5.5 V=15pF - 4.4 8.0 1.0 9.1 1.0 10.0 ns=50pF - 5.6 10.0 1.0 11.1 1.0 12.0 ns
ten enable time OE to Qn; see Figure12 [4]
VCC = 3.0 V to 3.6 V=15pF - 5.6 11.5 1.0 13.5 1.0 15.0 ns=50pF - 7.4 15.0 1.0 17.0 1.0 18.5 ns
VCC = 4.5 V to 5.5 V=15pF - 4.0 8.6 1.0 10.0 1.0 11.0 ns=50pF - 5.3 10.6 1.0 12.0 1.0 13.0 ns
tdis disable time OE to Qn; see Figure12 [5]
VCC = 3.0 V to 3.6 V=15pF - 5.4 11.0 1.0 13.0 1.0 14.5 ns=50pF - 8.7 15.7 1.0 16.2 1.0 17.5 ns
VCC = 4.5 V to 5.5 V=15pF - 3.8 8.0 1.0 9.5 1.0 10.5 ns=50pF - 5.8 10.3 1.0 11.0 1.0 12.0 ns
NXP Semiconductors 74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
fmax maximum
frequency
SHCP or STCP;
see Figure 8 and 9
VCC = 3.0 V to 3.6 V 80 125 - 60 - 40 - MHz
VCC = 4.5 V to 5.5 V 130 170 - 110 - 90 - MHz pulse width SHCP HIGH or LOW;
see Figure8
VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns
VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
STCP HIGH or LOW;
see Figure9
VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns
VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
MR LOW; see Figure11
VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns
VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
tsu set-up time DS to SHCP; see Figure9
VCC = 3.0 V to 3.6 V 3.5 - - 3.5 - 3.5 - ns
VCC = 4.5 V to 5.5 V 3.0 - - 3.0 - 3.0 - ns
SHCP to STCP;
see Figure10
VCC = 3.0 V to 3.6 V 8.5 - - 8.5 - 8.5 - ns
VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns hold time DS to SHCP; see Figure10
VCC = 3.0 V to 3.6 V 1.5 - - 1.5 - 1.5 - ns
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - ns
trec recovery
time
MR to SHCP; see Figure11
VCC = 3.0 V to 3.6 V 3.0 - - 3.0 - 3.0 - ns
VCC = 4.5 V to 5.5 V 2.5 - - 2.5 - 2.5 - ns
CPD power
dissipation
capacitance
fi = 1 MHz; VI =GNDto VCC [6]
[7] -180 - - - - - pF
74AHCT595; VCC = 4.5 V to 5.5 V
tpd propagation
delay
SHCPto Q7S; see Figure8 [2]=15pF - 3.8 8.2 1.0 9.0 1.0 10.0 ns=50pF - 5.2 10.0 1.0 11.0 1.0 12.0 ns
STCPto Qn; see Figure9 [2]=15pF - 4.0 7.4 1.0 8.5 1.0 9.5 ns=50pF - 5.3 9.0 1.0 10.5 1.0 11.5 nsto Q7S; see Figure11 [3]=15pF - 4.6 8.2 1.0 9.5 1.0 10.5 ns=50pF - 5.8 10.5 1.0 11.5 1.0 12.5 ns
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
NXP Semiconductors 74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
[1] Typical values are measured at nominal supply voltage.
[2] tpd is the same as tPHL and tPLH.
[3] tpd is the same as tPHL only.
[4] ten is the same as tPZL and tPZH.
[5] tdis is the same as tPLZ and tPHZ.
[6] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;
(CL VCC2fo)= sum of outputs;= output load capacitance inpF;
VCC= supply voltage inV.
[7] All 9 outputs switching.
ten enable time OE to Qn; see Figure12 [4]=15pF - 4.8 9.0 1.0 11.0 1.0 12.0 ns=50pF - 6.2 11.6 1.0 13.0 1.0 14.5 ns
tdis disable time OE to Qn; see Figure12 [5]=15pF - 3.6 6.9 1.0 8.0 1.0 9.0 ns=50pF - 5.8 10.3 1.0 11.0 1.0 12.0 ns
fmax maximum
frequency
SHCP and STCP;
see Figure 8 and 9
130 170 - 110 - 90 - MHz pulse width SHCP HIGH or LOW;
see Figure8
5.0 - - 5.0 - 5.0 - ns
STCP HIGH or LOW;
see Figure9
5.0 - - 5.0 - 5.0 - ns
MR LOW; see Figure11 5.0 - - 5.0 - 5.0 - ns
tsu set-up time DS to SHCP; see Figure9 3.0 - - 3.0 - 3.0 - ns
SHCP to STCP;
see Figure10
5.0 - - 5.0 - 5.0 - ns hold time DS to SHCP; see Figure10 2.0 - - 2.0 - 2.0 - ns
trec recovery
time
MR to SHCP; see Figure11 3.0 - - 3.0 - 3.0 - ns
CPD power
dissipation
capacitance
fi = 1 MHz; VI =GNDto VCC [6]
[7] -190 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.

Partno	Mfg	Dc	Qty	Available	Descript
74AHC595D	NXP	N/a	1745	avai	8-bit serial-in/serial-out or parallel-out shift register with output latches; 3-state