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74AHC3G14DP-74AHCT3G14DP
Triple inverting Schmitt trigger
1. General description
74AHC3G14 and 74AHCT3G14 are high-speed Si-gate CMOS devices. They provide
three inverting buffers with Schmitt trigger action. These devices are capable of
transforming slowly changing input signals into sharply defined, jitter-free output signals.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
2. Features and benefits Symmetrical output impedance High noise immunity ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101D exceeds 1000V Low power dissipation Balanced propagation delays Multiple package options Specified from 40 Cto+85 C and 40 Cto+125C
3. Applications Wave and pulse shaper for highly noisy environment Astable multivibrator Monostable multivibrator
74AHC3G14; 74AHCT3G14
Triple inverting Schmitt trigger
Rev. 8 — 13 May 2013 Product data sheet
NXP Semiconductors 74AHC3G14; 74AHCT3G14
Triple inverting Schmitt trigger
4. Ordering information
5. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6. Functional diagram
Table 1. Ordering information
74AHC3G14DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74AHCT3G14DP
74AHC3G14DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74AHCT3G14DC
74AHC3G14GT 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1 1.95 0.5 mm
SOT833-1
74AHCT3G14GT
74AHC3G14GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3  2  0.5 mm
SOT996-2
74AHCT3G14GD
Table 2. Marking codes
74AHC3G14DP A14
74AHCT3G14DP C14
74AHC3G14DC A14
74AHCT3G14DC C14
74AHC3G14GT A14
74AHCT3G14GT C14
74AHC3G14GD A14
74AHCT3G14GD C14
NXP Semiconductors 74AHC3G14; 74AHCT3G14
Triple inverting Schmitt trigger
7. Pinning information
7.1 Pinning
7.2 Pin description
Table 3. Pin description
1A, 2A, 3A 1, 3, 6 data input
GND 4 ground (0 V) , 2Y, 3Y 7, 5, 2 data output
VCC 8 supply voltage
NXP Semiconductors 74AHC3G14; 74AHCT3G14
Triple inverting Schmitt trigger
8. Functional description
[1] H= HIGH voltage level; L= LOW voltage level
9. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly at 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly at 8 mW/K.
For XSON8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
10. Recommended operating conditions
Table 4. Function table[1]
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VCC supply voltage 0.5 +7.0 V input voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V 20 - mA
IOK output clamping current VO < 0.5 V or VO >VCC +0.5V [1]- 20 mA output current 0.5 V < VO ICC supply current - 75 mA
IGND ground current 75 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40Cto +125 C [2]- 250 mW
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V input voltage 0 - 5.5 0 - 5.5 V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
NXP Semiconductors 74AHC3G14; 74AHCT3G14
Triple inverting Schmitt trigger
11. Static characteristicsTable 7. Static characteristics
Voltages are referenced to GND (ground = 0 V).
74AHC3G14
VOH HIGH-level
output voltage = VT+ or VT = 50 A; VCC= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V = 50 A; VCC= 3.0 V 2.9 3.0 - 2.9 - 2.9 - V = 50 A; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V = 4.0 mA; VCC= 3.0 V 2.58 - - 2.48 - 2.40 - V = 8.0 mA; VCC= 4.5 V 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage = VT+ or VT = 50 A; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V = 50 A; VCC= 3.0 V - 0 0.1 - 0.1 - 0.1 V = 50 A; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V = 4.0 mA; VCC= 3.0 V - - 0.36 - 0.44 - 0.55 V = 8.0 mA; VCC= 4.5 V - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5Vor GND;
VCC =0 Vto 5.5V - 0.1 - 1.0 - 2.0 A
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5 V - 1.0 - 10 - 40 A input
capacitance 1.5 10 - 10 - 10 pF
74AHCT3G14
VOH HIGH-level
output voltage = VT+ or VT; VCC= 4.5 V = 50A 4.4 4.5 - 4.4 - 4.4 - V = 8.0 mA 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage = VT+ or VT; VCC= 4.5 V = 50A - 0 0.1 - 0.1 - 0.1 V = 8.0 mA - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5Vor GND;
VCC =0 Vto 5.5V - 0.1 - 1.0 - 2.0 A
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5 V - 1.0 - 10 - 40 A
ICC additional
supply current
per input pin; VI =3.4V;
other inputs at VCCor GND; =0 A; VCC = 5.5 V - 1.35 - 1.5 - 1.5 mA input
capacitance 1.5 10 - 10 - 10 pF
NXP Semiconductors 74AHC3G14; 74AHCT3G14
Triple inverting Schmitt trigger
11.1 Transfer characteristics
12. Dynamic characteristics
Table 8. Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V). See Figure 9 and Figure 10.
74AHC3G14
VT+ positive-going
threshold
voltage
VCC = 3.0 V - - 2.2 - 2.2 - 2.2 V
VCC = 4.5 V - - 3.15 - 3.15 - 3.15 V
VCC = 5.5 V - - 3.85 - 3.85 - 3.85 V
VT negative-going
threshold
voltage
VCC = 3.0 V 0.9 - - 0.9 - 0.9 - V
VCC = 4.5 V 1.35 - - 1.35 - 1.35 - V
VCC = 5.5 V 1.65 - - 1.65 - 1.65 - V hysteresis
voltage
VCC = 3.0 V 0.3 - 1.2 0.3 1.2 0.25 1.2 V
VCC = 4.5 V 0.4 - 1.4 0.4 1.4 0.35 1.4 V
VCC = 5.5 V 0.5 - 1.6 0.5 1.6 0.45 1.6 V
74AHCT3G14
VT+ positive-going
threshold
voltage
VCC = 4.5 V - - 2.0 - 2.0 - 2.0 V
VCC = 5.5 V - - 2.0 - 2.0 - 2.0 V
VT negative-going
threshold
voltage
VCC = 4.5 V 0.5 - - 0.5 - 0.5 - V
VCC = 5.5 V 0.6 - - 0.6 - 0.6 - V hysteresis
voltage
VCC = 4.5 V 0.4 - 1.4 0.4 1.4 0.35 1.4 V
VCC = 5.5 V 0.4 - 1.6 0.4 1.6 0.35 1.6 V
Table 9. Dynamic characteristics
GND = 0 V; tr = tf  3.0 ns; for test circuit see Figure8.
74AHC3G14
tpd propagation
delay
nA to nY; see Figure7 [1]
VCC = 3.0 V to 3.6 V [2]= 15 pF - 4.2 12.8 1.0 15.0 1.0 16.5 ns= 50 pF - 6.0 16.3 1.0 18.5 1.0 20.5 ns
VCC = 4.5 V to 5.5 V [3]= 15 pF - 3.2 8.6 1.0 10.0 1.0 11.0 ns= 50 pF - 4.6 10.6 1.0 12.0 1.0 13.5 ns
CPD power
dissipation
capacitance
per buffer; =50pF;fi =1 MHz; =GNDto VCC
[4] -10- - - - - pF
NXP Semiconductors 74AHC3G14; 74AHCT3G14
Triple inverting Schmitt trigger
[1] tpd is the same as tPLH and tPHL.
[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4] CPD is used to determine the dynamic power dissipation PD (W). =CPD VCC2fi+(CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;
(CL VCC2fo)= sum of the outputs.
13. Waveforms
74AHCT3G14
tpd propagation
delay
nA to nY;
VCC= 4.5Vto 5.5V
[1]
[3]= 15 pF - 4.1 7.0 1.0 8.0 1.0 9.0 ns= 50 pF - 5.9 8.5 1.0 10.0 1.0 11.0 ns
CPD power
dissipation
capacitance
per buffer; =50pF;fi =1 MHz; =GNDto VCC
[4] -12- - - - - pF
Table 9. Dynamic characteristics …continued
GND = 0 V; tr = tf  3.0 ns; for test circuit see Figure8.
Table 10. Test data
74AHC3G14 GND to VCC 0.5  VCC 0.5  VCC
74AHCT3G14 GND to 3.0 V 1.5 V 0.5  VCC
NXP Semiconductors 74AHC3G14; 74AHCT3G14
Triple inverting Schmitt trigger
13.1 Transfer characteristic waveforms
NXP Semiconductors 74AHC3G14; 74AHCT3G14
Triple inverting Schmitt trigger
NXP Semiconductors 74AHC3G14; 74AHCT3G14
Triple inverting Schmitt trigger
14. Application information
The slow input rise and fall times cause additional power dissipation, which can be
calculated using the following formula:
Padd =fi(tr ICC(AV) +tf ICC(AV)) VCC where:
Padd= additional power dissipation (W);= input frequency (MHz);= input rise time (ns); 10 %to 90 %;= input fall time (ns); 90 %to 10 %;
ICC(AV)= average additional supply current (A).
ICC(AV) differs with positive or negative input transitions, as shown in Figure 16
and Figure 17.
For 74AHC3G14 and 74AHCT3G14 used in relaxation oscillator circuit, see Figure 18.
Note to the application information: All values given are typical unless otherwise specified.

Partno	Mfg	Dc	Qty	Available	Descript
74AHC3G14DP	NXP/PHIL	N/a	9000	avai	74AHC3G14; 74AHCT3G14; Inverting Schmitt trigger
74AHCT3G14DP	NXP/PHIL	N/a	12000	avai	Triple inverting Schmitt trigger