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74AHC374D-74AHC374PW-74AHCT374PW
Octal D-type flip-flop; positive edge-trigger; 3-state
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state 74AHC374;
74AHCT374
FEATURES ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000V EIA/JESD22-A115-A
exceeds 200V
CDM EIA/JESD22-C101
exceeds 1000V Balanced propagation delays All inputs have Schmitt-trigger
actions Inputs acceptsvoltageshigher than
VCC Common 3-state output enable
input ICC category: MSI For AHC only:
operates with CMOS input levels For AHCT only:
operates with TTL input levels Specified from
−40to +85 and +125 °C.
DESCRIPTIONThe 74AHC/AHCT374 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT374 are octal D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications. clock (CP) and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs.
When OEis HIGH, the outputsgoto the high-impedance OFF-state. Operation
of the OE input does not affect the state of the flip-flops.
The ‘374’ is functionally identical to the ‘534’, but has non-inverting outputs.
QUICK REFERENCE DATAGND=0 V; Tamb =25 °C; tr =tf≤ 3.0 ns.
Notes CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi+∑ (CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz; (CL× VCC2×fo)= sum of outputs;= output load capacitance in pF;
VCC= supply voltage in Volts. The condition is VI= GNDto VCC.
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state 74AHC374;
74AHCT374
FUNCTION TABLESee note1.
Note H= HIGH voltage level;= HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;= LOW voltage level;= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;= don’t care;= high-impedance OFF-state;= LOW-to-HIGH CP transition.
ORDERING INFORMATION
PINNING
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state 74AHC374;
74AHCT374
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state 74AHC374;
74AHCT374
LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground=0V).
Notes The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state 74AHC374;
74AHCT374
DC CHARACTERISTICS
74AHC familyOver recommended operating conditions; voltages are referenced to GND (ground=0V).
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state 74AHC374;
74AHCT374
74AHCT familyOver recommended operating conditions; voltages are referenced to GND (ground=0V).
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state 74AHC374;
74AHCT374
AC CHARACTERISTICS
Type 74AHC374GND=0 V; tr =tf≤ 3.0 ns.
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state 74AHC374;
74AHCT374
Notes Typical values at VCC= 3.3V. Typical values at VCC= 5.0V.
