74AHC373D-74AHCT373D-74AHCT373PW Fast Delivery |IC PHOENIX CO.,LIMITED

74AHC373D ,Octal D-type transparent latch; 3-stateFeaturesn Balanced propagation delaysn All inputs have a Schmitt-trigger actionn Common 3-state out ..
74AHC373PW ,Octal D-type transparent latch; 3-state
74AHC373PW ,Octal D-type transparent latch; 3-state
74AHC374 ,3-state
74AHC374D ,Octal D-type flip-flop; positive edge-trigger; 3-stateINTEGRATED CIRCUITSDATA SHEET74AHC374; 74AHCT374Octal D-type flip-flop; positiveedge-trigger; 3-sta ..
74AHC374PW ,Octal D-type flip-flop; positive edge-trigger; 3-stateFEATURES DESCRIPTION• ESD protection: The 74AHC/AHCT374 are high-speed Si-gate CMOS devices and are ..
74HC373D ,74HC/HCT373; Octal D-type transparent latch; 3-stateLogic diagram (one latch) D0 D1 D2 D3 D4 D5 D6 D7D Q D Q D Q D Q D Q D Q D Q D QLATCH LATCH LATCH L ..
74HC373DB ,74HC/HCT373; Octal D-type transparent latch; 3-stateapplications. A latch enable (LE)QUICK REFERENCE DATAGND = 0 V; T =25 °C; t =t = 6 nsamb r fTYPICAL ..
74HC373DB ,74HC/HCT373; Octal D-type transparent latch; 3-stateFEATURES input and an output enable (OE) input are common to alllatches.• 3-state non-inverting out ..
74HC373DB ,74HC/HCT373; Octal D-type transparent latch; 3-stateLogic diagram (one latch) D0 D1 D2 D3 D4 D5 D6 D7D Q D Q D Q D Q D Q D Q D Q D QLATCH LATCH LATCH L ..
74HC373N ,Octal D-type transparent latch; 3-stateGeneral descriptionThe 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible ..
74HC373PW ,74HC/HCT373; Octal D-type transparent latch; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..

74AHC373D-74AHCT373D-74AHCT373PW
Octal D-type transparent latch; 3-state
General descriptionThe 74AHC373; 74AHCT373isa high-speed Si-gate CMOS device andis pin compatible
with Low-power Schottky TTL (LSTTL).Itis speciﬁedin compliance with JEDEC standard
No. 7-A.
The 74AHC373; 74AHCT373 consists of eight D-type transparent latches featuring
separate D-type inputs for each latch and 3-state true outputs for bus oriented
applications.A latch enable input (LE) andan output enable input (OE) are commontoall
latches.
When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
Dn input changes. When pin LE is LOW, the latches store the information that is present
at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.
When pin OE is LOW, the contents of the 8 latches are available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the latches.
The 74AHC373; 74AHCT373 is functionally identical to the 74AHC573; 74AHCT573, but
has a different pin arrangement. Features Balanced propagation delays All inputs have a Schmitt-trigger action Common 3-state output enable input Inputs accepts voltages higher than VCC Functionally identical to the 74AHC573; 74AHCT573 Input levels: For 74AHC373: CMOS input level For 74AHCT373: TTL input level ESD protection: HBM EIA/JESD22-A114E exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V CDM EIA/JESD22-C101C exceeds 1000V Multiple package options Speciﬁed from −40 °C to +85 °C and from −40 °C to +125°C
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
Rev. 03 — 20 May 2008 Product data sheet
NXP Semiconductors 74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state Ordering information Functional diagram
Table 1. Ordering information
74AHC373
74AHC373D −40°Cto +125°C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74AHC373PW −40°Cto +125°C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74AHCT373
74AHCT373D −40°Cto +125°C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74AHCT373PW −40°Cto +125°C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
NXP Semiconductors 74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
NXP Semiconductors 74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 3-state output enable input (active LOW) 2 3-state latch output 3 data input 4 data input 5 3-state latch output 6 3-state latch output 7 data input 8 data input 9 3-state latch output
GND 10 ground (0V) 11 latch enable input (active HIGH) 12 3-state latch output 13 data input 14 data input 15 3-state latch output 16 3-state latch output 17 data input
NXP Semiconductors 74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state Functional description
[1]H= HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;= LOW voltage level;= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;= high-impedance OFF-state. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. 18 data input 19 3-state latch output
VCC 20 supply voltage
Table 2. Pin description …continued
Table 3. Function table[1]
Enable and read register (transparent mode) L H L L L
HHH
Latch and read register L L l L L H
Latch register and disable outputs H XXXZ
XXZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5V [1] −20 - mA
IOK output clamping current VO< −0.5 V orVO >VCC+ 0.5V [1] −20 +20 mA output current VO = −0.5 V to (VCC+ 0.5V) −25 +25 mA
ICC supply current - +75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125°C [2]- 500 mW
NXP Semiconductors 74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state Recommended operating conditions Static characteristics
Table 5. Operating conditions
74AHC373
VCC supply voltage 2.0 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 3.0 V to 3.6V - - 100 ns/V
VCC = 4.5 V to 5.5V - - 20 ns/V
74AHCT373
VCC supply voltage 4.5 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 4.5 V to 5.5V - - 20 ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
74AHC373
VIH HIGH-level
input voltage
VCC = 2.0V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage
VCC = 2.0V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage = VIH or VIL= −50 μA; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= −50 μA; VCC= 3.0V 2.9 3.0 - 2.9 - 2.9 - V= −50 μA; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= −4.0 mA; VCC= 3.0V 2.58 - - 2.48 - 2.40 - V= −8.0 mA; VCC= 4.5V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL = 50 μA; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 3.0V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V = 4.0 mA; VCC= 3.0V - - 0.36 - 0.44 - 0.55 V = 8.0 mA; VCC= 4.5V - - 0.36 - 0.44 - 0.55 V
NXP Semiconductors 74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
IOZ OFF-state
output current
VI =VIH or VIL; =VCCor GND;
VCC= 5.5V ±0.2 ±2.5 - ±10.0 μA input leakage
current =VCCor GND;
VCC=0V to 5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply current VI =VCCor GND;IO =0A;
VCC= 5.5V - 4.0 - 40 - 80 μA input
capacitance =VCCor GND - 3 10 - 10 - 10 pF output
capacitance 4 - - - - 10 pF
74AHCT373
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage = VIH or VIL; VCC= 4.5V= −50μA 4.4 4.5 - 4.4 - 4.4 - V= −8.0 mA 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL; VCC= 4.5V = 50μA - 0 0.1 - 0.1 - 0.1 V = 8.0 mA - - 0.36 - 0.44 - 0.55 V
IOZ OFF-state
output current
VI =VIH or VIL; =VCCor GND per input
pin; other inputs at VCC or
GND; IO=0 A; VCC= 5.5V ±0.2 ±2.5 - ±10.0 μA input leakage
current= 5.5 Vor GND;
VCC=0V to 5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply current VI =VCCor GND; IO = 0A;
VCC= 5.5V - 4.0 - 40 - 80 μA
ΔICC additional
supply current
per input pin; =VCC− 2.1V; other pinsat
VCC or GND; IO =0A;
VCC= 4.5Vto 5.5V - 1.35 - 1.5 - 1.5 μA input
capacitance =VCCor GND - 3 10 - 10 - 10 pF output
capacitance 4 - - - - 10 pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
NXP Semiconductors 74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
74AHC373
tpd propagation
delayto Qn; see Figure7 [2]
VCC = 3.0 V to 3.6V=15pF - 6.0 11.4 1.0 13.5 1.0 14.5 ns=50pF - 7.8 14.9 1.0 17.0 1.0 19.0 ns
VCC = 4.5 V to 5.5V=15pF - 4.0 7.2 1.0 8.5 1.0 9.0 ns=50pF - 5.3 9.2 1.0 10.5 1.0 11.5 nsto Qn; see Figure8 [2]
VCC = 3.0 V to 3.6V=15pF - 6.3 11.0 1.0 13.0 1.0 14.0 ns=50pF - 8.3 14.5 1.0 16.5 1.0 18.5 ns
VCC = 4.5 V to 5.5V=15pF - 4.3 7.2 1.0 8.5 1.0 9.0 ns=50pF - 5.6 9.7 1.0 11.1 1.0 12.5 ns
ten enable time OEto Qn; see Figure9 [3]
VCC = 3.0 V to 3.6V=15pF - 5.6 11.4 1.0 13.5 1.0 14.5 ns=50pF - 7.5 14.9 1.0 17.0 1.0 19.0 ns
VCC = 4.5 V to 5.5V=15pF - 3.8 8.1 1.0 9.5 1.0 10.5 ns=50pF - 5.2 10.1 1.0 11.5 1.0 13.0 ns
tdis disable time OEto Qn; see Figure9 [4]
VCC = 3.0 V to 3.6V=15pF - 5.6 10.0 1.0 12.0 1.0 13.0 ns=50pF - 9.2 13.3 1.0 15.0 1.0 17.0 ns
VCC = 4.5 V to 5.5V=15pF - 4.3 7.2 1.0 8.5 1.0 9.5 ns=50pF - 6.4 9.2 1.0 10.5 1.0 11.5 ns pulse width LE HIGH or LOW;
see Figure8
VCC= 3.0 V to 3.6V 5.0 - - 5.0 - 5.0 - ns
VCC= 4.5 V to 5.5V 5.0 - - 5.0 - 5.0 - ns
tsu set-up time Dnto LE; see Figure10
VCC= 3.0 V to 3.6V 4.0 - - 4.0 - 4.0 - ns
VCC= 4.5 V to 5.5V 4.0 - - 4.0 - 4.0 - ns
NXP Semiconductors 74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0V).
[2] tpd is the same as tPHL and tPLH.
[3] ten is the same as tPZH and tPZL.
[4] tdis is the same as tPHZ and tPLZ.
[5] CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where: = input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs. hold time Dn to LE; see Figure10
VCC= 3.0 V to 3.6V 1.0 - - 1.0 - 1.0 - ns
VCC= 4.5 V to 5.5V 1.0 - - 1.0 - 1.0 - ns
CPD power
dissipation
capacitance
fi = 1 MHz;= GNDto VCC
[5] -10 - - - - - pF
74AHCT373; VCC = 4.5 V to 5.5V
tpd propagation
delayto Qn; see Figure7 [4]=15pF - 4.0 8.5 1.0 9.5 1.0 11.0 ns=50pF - 5.2 9.5 1.0 10.5 1.0 12.0 nsto Qn; see Figure8 =15pF [4] - 4.3 12.3 1.0 13.5 1.0 15.5 ns=50pF - 5.5 13.3 1.0 14.5 1.0 17.0 ns
ten enable time OEto Qn; see Figure9=15pF - 4.0 10.9 1.0 12.5 1.0 14.0 ns =50pF [4] - 5.2 11.9 1.0 13.5 1.0 15.0 ns
tdis disable time OEto Qn; see Figure9=15pF - 4.4 10.2 1.0 11.0 1.0 13.0 ns=50pF - 6.5 11.2 1.0 12.0 1.0 14.0 ns pulse width LE HIGH; see Figure8 [4] 6.5 - - 6.5 - 6.5 - ns
tsu set-up time Dnto LE; see Figure10 3.5 - - 3.5 - 3.5 - ns hold time Dn to LE; see Figure10 1.5 - - 1.5 - 1.5 - ns
CPD power
dissipation
capacitance
fi = 1 MHz;= GNDto VCC
[5] -12 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.

Partno	Mfg	Dc	Qty	Available	Descript
74AHC373D	NXP ?	N/a	20000	avai	Octal D-type transparent latch; 3-state
74AHCT373D	NXP	N/a	2000	avai	Octal D-type transparent latch; 3-state
74AHCT373PW	NXP	N/a	2500	avai	Octal D-type transparent latch; 3-state