74AHC32D-74AHC32PW -74AHCT32PW Fast Delivery |IC PHOENIX CO.,LIMITED

74AHC32PW ,Quad 2-input OR gate74AHC32; 74AHCT32Quad 2-input OR gateRev. 04 — 22 May 2008 Product data sheet1.
74AHC32PW ,Quad 2-input OR gateINTEGRATED CIRCUITSDATA SHEET74AHC32; 74AHCT32Quad 2-input OR gateProduct speciﬁcation 1999 Sep 27S ..
74AHC373 ,3-state
74AHC373D ,Octal D-type transparent latch; 3-stateFeaturesn Balanced propagation delaysn All inputs have a Schmitt-trigger actionn Common 3-state out ..
74AHC373PW ,Octal D-type transparent latch; 3-state
74AHC373PW ,Octal D-type transparent latch; 3-state
74HC373D ,74HC/HCT373; Octal D-type transparent latch; 3-stateLogic diagram (one latch) D0 D1 D2 D3 D4 D5 D6 D7D Q D Q D Q D Q D Q D Q D Q D QLATCH LATCH LATCH L ..
74HC373DB ,74HC/HCT373; Octal D-type transparent latch; 3-stateapplications. A latch enable (LE)QUICK REFERENCE DATAGND = 0 V; T =25 °C; t =t = 6 nsamb r fTYPICAL ..
74HC373DB ,74HC/HCT373; Octal D-type transparent latch; 3-stateFEATURES input and an output enable (OE) input are common to alllatches.• 3-state non-inverting out ..
74HC373DB ,74HC/HCT373; Octal D-type transparent latch; 3-stateLogic diagram (one latch) D0 D1 D2 D3 D4 D5 D6 D7D Q D Q D Q D Q D Q D Q D Q D QLATCH LATCH LATCH L ..
74HC373N ,Octal D-type transparent latch; 3-stateGeneral descriptionThe 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible ..
74HC373PW ,74HC/HCT373; Octal D-type transparent latch; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..

74AHC32D-74AHC32PW -74AHCT32PW
Quad 2-input OR gate
General descriptionThe 74AHC32; 74AHCT32 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL).Itis speciﬁedin compliance with JEDEC standard
No. 7-A.
The 74AHC32; 74AHCT32 provides the 2-input OR function. Features Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Input levels: For 74AHC32: CMOS level For 74AHCT32: TTL level ESD protection: HBM EIA/JESD22-A114E exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V CDM EIA/JESD22-C101C exceeds 1000V Multiple package options Speciﬁed from −40 °C to +85 °C and from −40 °C to +125°C Ordering information
74AHC32; 74AHCT32
Quad 2-input OR gate
Rev. 04 — 22 May 2008 Product data sheet
Table 1. Ordering information
74AHC32
74AHC32D −40 °C to +125°C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74AHC32PW −40 °C to +125°C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74AHC32BQ −40 °C to +125°C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad ﬂat package; no leads; 14 terminals;
body 2.5×3× 0.85 mm
SOT762-1
NXP Semiconductors 74AHC32; 74AHCT32
Quad 2-input OR gate Functional diagram
74AHCT32
74AHCT32D −40 °C to +125°C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74AHCT32PW −40 °C to +125°C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74AHCT32BQ −40 °C to +125°C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad ﬂat package; no leads; 14 terminals;
body 2.5×3× 0.85 mm
SOT762-1
Table 1. Ordering information …continued
NXP Semiconductors 74AHC32; 74AHCT32
Quad 2-input OR gate Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 data input 2 data input 3 data output 4 data input 5 data input 6 data output
GND 7 ground (0V) 8 data output 9 data input 10 data input 11 data output 12 data input 13 data input
VCC 14 supply voltage
NXP Semiconductors 74AHC32; 74AHCT32
Quad 2-input OR gate Functional description
[1]H= HIGH voltage level;= LOW voltage level;= don’t care. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K. Recommended operating conditions
Table 3. Function table[1]
LLL H H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5V [1] −20 - mA
IOK output clamping current VO < −0.5 V or VO > VCC + 0.5V [1] −20 +20 mA output current VO = −0.5 V to (VCC + 0.5V) −25 +25 mA
ICC supply current - +75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb= −40°Cto +125°C [2]- 500 mW
Table 5. Operating conditions
74AHC32
VCC supply voltage 2.0 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC= 3.0Vto 3.6V - - 100 ns/V
VCC= 4.5Vto 5.5V - - 20 ns/V
NXP Semiconductors 74AHC32; 74AHCT32
Quad 2-input OR gate Static characteristics
74AHCT32
VCC supply voltage 4.5 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC= 4.5Vto 5.5V - - 20 ns/V
Table 5. Operating conditions …continued
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
74AHC32
VIH HIGH-level
input voltage
VCC= 2.0V 1.5 - - 1.5 - 1.5 - V
VCC= 3.0V 2.1 - - 2.1 - 2.1 - V
VCC= 5.5V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage
VCC= 2.0V - - 0.5 - 0.5 - 0.5 V
VCC= 3.0V - - 0.9 - 0.9 - 0.9 V
VCC= 5.5V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage =VIH orVIL= −50 μA; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= −50 μA; VCC= 3.0V 2.9 3.0 - 2.9 - 2.9 - V= −50 μA; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= −4.0 mA; VCC= 3.0V 2.58 - - 2.48 - 2.40 - V= −8.0 mA; VCC= 4.5V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage =VIHorVIL =50 μA; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =50 μA; VCC= 3.0V - 0 0.1 - 0.1 - 0.1 V =50 μA; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V= 4.0 mA; VCC= 3.0V - - 0.36 - 0.44 - 0.55 V= 8.0 mA; VCC= 4.5V - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5Vor GND;
VCC=0Vto 5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply current VI =VCCor GND; IO =0A;
VCC= 5.5V - 2.0 - 20 - 40 μA input
capacitance =VCCor GND - 3 10 - 10 - 10 pF output
capacitance 4 - - --- pF
NXP Semiconductors 74AHC32; 74AHCT32
Quad 2-input OR gate
10. Dynamic characteristics
74AHCT32
VIH HIGH-level
input voltage
VCC = 4.5Vto 5.5V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5Vto 5.5V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC= 4.5V= −50μA 4.4 4.5 - 4.4 - 4.4 - V= −8.0 mA 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage =VIHor VIL; VCC= 4.5V =50μA - 0 0.1 - 0.1 - 0.1 V= 8.0 mA - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5Vor GND;
VCC=0Vto 5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply current VI =VCCor GND; IO =0A;
VCC= 5.5V - 2.0 - 20 - 40 μA
ΔICC additional
supply current
per input pin; =VCC− 2.1 V; other pins
at VCCor GND; IO =0A;
VCC= 4.5Vto 5.5V - 1.35 - 1.5 - 1.5 mA input
capacitance =VCCor GND - 3 10 - 10 - 10 pF output
capacitance 4 - - --- pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure7.
74AHC32
tpd propagation
delay
nA, nB to nY; see Figure6 [2]
VCC= 3.0Vto 3.6V=15pF - 3.9 7.9 1.0 9.5 1.0 10.0 ns=50pF - 5.6 11.4 1.0 13 1.0 14.5 ns
VCC= 4.5Vto 5.5V=15pF - 2.8 5.5 1.0 6.5 1.0 7.0 ns=50pF - 4.1 7.5 1.0 8.5 1.0 9.5 ns
CPD power
dissipation
capacitance=1 MHz; VI= GNDto VCC [3] -10 - - - - - pF
NXP Semiconductors 74AHC32; 74AHCT32
Quad 2-input OR gate
[1] Typical values are measured at nominal supply voltage (VCC=3.3 V and VCC=5.0V).
[2] tpd is the same as tPLH and tPHL.
[3] CPDis used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs.
11. Waveforms
74AHCT32; VCC= 4.5Vto 5.5V
tpd propagation
delay
nA, nB to nY; see Figure6 [2]=15pF - 3.1 6.9 1.0 8.0 1.0 9.0 ns=50pF - 4.3 7.9 1.0 9.0 1.0 10.0 ns
CPD power
dissipation
capacitance=1 MHz; VI= GNDto VCC [3] -12 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure7.
Table 8. Measurement points
74AHC32 0.5× VCC 0.5× VCC
74AHCT32 1.5V 0.5× VCC

Partno	Mfg	Dc	Qty	Available	Descript
74AHC32D	NXP	N/a	1136	avai	Quad 2-input OR gate
74AHC32PW	NXP	N/a	22500	avai	Quad 2-input OR gate
74AHCT32PW		N/a	10000	avai	Quad 2-input OR gate