74AHC273BQ-74AHC273PW-74AHCT273PW Fast Delivery |IC PHOENIX CO.,LIMITED

74AHCT273PW ,Octal D-type flip-flop with reset; positive-edge triggerapplications where only the true output is required and the clockand master reset are common to all ..
74AHCT2G08DC ,Dual 2-input AND gateFeatures and benefits Symmetrical output impedance High noise immunity ESD protection: HBM JESD ..
74AHCT2G08DP ,74AHC2G08; 74AHCT2G08; Dual 2-input AND gateFeatures■ Symmetrical output impedance■ High noise immunity■ ESD protection:◆ HBM EIA/JESD22-A114-B ..
74AHCT2G08DP ,74AHC2G08; 74AHCT2G08; Dual 2-input AND gateLogic diagram (one gate).74AHC_AHCT2G08 All information provided in this document is subject to leg ..
74AHCT2G125DC ,Bus buffer/line driver 3-stateFeatures and benefits Symmetrical output impedance High noise immunity Low power dissipation Ba ..
74AHCT2G125DP ,Bus buffer/line driver 3-stateINTEGRATED CIRCUITSDATA SHEET74AHC2G125; 74AHCT2G125Bus buffer/line driver; 3-stateProduct speciﬁca ..
74HC4016PW ,74HC/HCT4016; Quad bilateral switchesINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC4017D ,Johnson decade counter with 10 decoded outputsGeneral descriptionThe 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded outp ..
74HC4017N ,74HC/HCT4017; Johnson decade counter with 10 decoded outputsGENERAL DESCRIPTIONtable).The 74HC/HCT4017 are high-speed Si-gate CMOSWhen cascading counters, the ..
74HC4017PW ,74HC/HCT4017; Johnson decade counter with 10 decoded outputsFeatures and benefits Wide supply voltage range from 2.0 V to 6.0 V Input levels: For 74HC4017: ..
74HC4020 ,14-stage binary ripple counter
74HC4020 ,14-stage binary ripple counter

74AHC273BQ-74AHC273PW-74AHCT273PW
Octal D-type flip-flop with reset; positive-edge trigger
General descriptionThe 74AHC273; 74AHCT273isa high-speed Si-gate CMOS device andis pin compatible
with Low-power Schottky TTL (LSTTL).Itis speciﬁedin compliance with JEDEC standard
No. 7-A.
The 74AHC273; 74AHCT273 has eight edge-triggered, D-type ﬂip-ﬂops with individual D
inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs, load and reset (clear) all ﬂip-ﬂops
simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the ﬂip-ﬂop.
All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR
input.
The device is useful for applications where only the true output is required and the clock
and master reset are common to all storage elements. Features Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Ideal buffer for MOS microcontroller or memory Common clock and master reset Related product versions: 74AHC377; 74AHCT377 for clock enable version 74AHC373; 74AHCT373 for transparent latch version 74AHC374; 74AHCT374 for 3-state version Input levels: For 74AHC273: CMOS level For 74AHCT273: TTL level ESD protection: HBM EIA/JESD22-A114E exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V CDM EIA/JESD22-C101C exceeds 1000V Multiple package options Speciﬁed from −40 °C to +85 °C and from −40 °C to +125°C
74AHC273; 74AHCT273
Octal D-type ﬂip-ﬂop with reset; positive-edge trigger
Rev. 03 — 13 May 2008 Product data sheet
NXP Semiconductors 74AHC273; 74AHCT273
Octal D-type ﬂip-ﬂop with reset; positive-edge trigger Ordering information Functional diagram
Table 1. Ordering information
74AHC273
74AHC273D −40 °C to +125°C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74AHC273PW −40 °C to +125°C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74AHC273BQ −40 °C to +125°C DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad ﬂat package; no leads; 20 terminals; body
2.5 × 4.5 × 0.85 mm
SOT764-1
74AHCT273
74AHCT273D −40 °C to +125°C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74AHCT273PW −40 °C to +125°C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74AHCT273BQ −40 °C to +125°C DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad ﬂat package; no leads; 20 terminals; body
2.5 × 4.5 × 0.85 mm
SOT764-1
NXP Semiconductors 74AHC273; 74AHCT273
Octal D-type ﬂip-ﬂop with reset; positive-edge trigger
NXP Semiconductors 74AHC273; 74AHCT273
Octal D-type ﬂip-ﬂop with reset; positive-edge trigger Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 master reset input (active LOW) 2 ﬂip-ﬂop output 3 data input 4 data input 5 ﬂip-ﬂop output 6 ﬂip-ﬂop output 7 data input 8 data input 9 ﬂip-ﬂop output
GND 10 ground (0V) 11 clock input (LOW-to-HIGH edge-triggered) 12 ﬂip-ﬂop output 13 data input 14 data input 15 ﬂip-ﬂop output 16 ﬂip-ﬂop output
NXP Semiconductors 74AHC273; 74AHCT273
Octal D-type ﬂip-ﬂop with reset; positive-edge trigger Functional description
[1]H= HIGH voltage level;= HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;= LOW voltage level;= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;= LOW-to-HIGH;= don’t care. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN20 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K. 17 data input 18 data input 19 ﬂip-ﬂop output
VCC 20 supply voltage
Table 2. Pin description …continued
Table 3. Function table[1]
Reset (clear) L X X L
Load ‘1’ H ↑ hH
Load ‘0’ H ↑ lL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V [1] −20 - mA
IOK output clamping current VO < −0.5 V orVO >VCC+ 0.5V [1] −20 +20 mA output current VO = −0.5Vto (VCC+ 0.5V) −25 +25 mA
ICC supply current - +75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125°C [2]- 500 mW
NXP Semiconductors 74AHC273; 74AHCT273
Octal D-type ﬂip-ﬂop with reset; positive-edge trigger Recommended operating conditions Static characteristics
Table 5. Operating conditions
74AHC273
VCC supply voltage 2.0 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V
VCC = 4.5 V to 5.5 V - - 20 ns/V
74AHCT273
VCC supply voltage 4.5 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 4.5 V to 5.5 V - - 20 ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
74AHC273
VIH HIGH-level
input voltage
VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage
VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage = VIH or VIL= −50 μA; VCC= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V= −50 μA; VCC= 3.0 V 2.9 3.0 - 2.9 - 2.9 - V= −50 μA; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V= −4.0 mA; VCC= 3.0 V 2.58 - - 2.48 - 2.40 - V= −8.0 mA; VCC= 4.5 V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL = 50 μA; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 3.0 V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V = 4.0 mA; VCC= 3.0 V - - 0.36 - 0.44 - 0.55 V = 8.0 mA; VCC= 4.5 V - - 0.36 - 0.44 - 0.55 V
NXP Semiconductors 74AHC273; 74AHCT273
Octal D-type ﬂip-ﬂop with reset; positive-edge trigger input leakage
current= 5.5 Vor GND;
VCC =0Vto5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5V - 4.0 - 40 - 80 μA input
capacitance 3 10 - 10 - 10 pF output
capacitance - - - - - pF
74AHCT273
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage = VIH or VIL; VCC= 4.5 V= −50μA 4.4 - - 4.4 - 4.4 - V= −8.0 mA 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL; VCC= 4.5 V = 50μA - 0 0.1 - 0.1 - 0.1 V = 8.0 mA - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5 Vor GND;
VCC =0Vto5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5V - 4.0 - 40 - 80 μA
ΔICC additional
supply current
per input pin; =VCC− 2.1 V; other pins
at VCCor GND; IO =0A;
VCC = 4.5 V to 5.5 V - 1.35 - 1.5 - 1.5 mA input
capacitance 3 10 - 10 - 10 pF output
capacitance - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74AHC273; 74AHCT273
Octal D-type ﬂip-ﬂop with reset; positive-edge trigger
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
74AHC273
tpd propagation
delayto Qn; see Figure7 [2]
VCC = 3.0 V to 3.6 V=15pF - 6.0 13.6 1.0 16.0 1.0 17.0 ns=50pF - 8.6 17.1 1.0 19.5 1.0 21.5 ns
VCC = 4.5 V to 5.5 V=15pF - 4.2 9 1.0 10.5 1.0 11.5 ns=50pF - 6.0 11.0 1.0 12.5 1.0 14.0 nsto Qn; see Figure8 [3]
VCC = 3.0 V to 3.6 V=15pF - 5.1 13.6 1.0 16.0 1.0 17.0 ns=50pF - 7.3 17.1 1.0 19.5 1.0 21.5 ns
VCC = 4.5 V to 5.5 V=15pF - 3.7 8.5 1.0 10.0 1.0 11.0 ns=50pF - 5.3 10.5 1.0 12.0 1.0 13.5 ns
fmax maximum
frequency
see Figure7
VCC = 3.0 V to 3.6 V=15pF 75 120 - 65 - 65 - MHz=50pF 50 75 - 45 - 45 - MHz
VCC = 4.5 V to 5.5 V=15pF 120 165 - 100 - 100 - MHz=50pF 80 110 - 70 - 70 - MHz pulse width CP HIGH or LOW;
see Figure7
VCC = 3.0 V to 3.6 V 5.0 - - 6.5 - 6.5 - ns
VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
MR LOW; see Figure8
VCC = 3.0 V to 3.6 V 5.0 - - 6.0 - 6.0 - ns
VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
tsu set-up time Dn to CP; see Figure9
VCC = 3.0 V to 3.6 V 3.0 - - 3.0 - 3.0 - ns
VCC = 4.5 V to 5.5 V 3.0 - - 3.0 - 3.0 - ns hold time Dn to CP; see Figure9
VCC = 3.0 V to 3.6 V 1.0 - - 1.0 - 1.0 - ns
VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - 1.0 - ns
NXP Semiconductors 74AHC273; 74AHCT273
Octal D-type ﬂip-ﬂop with reset; positive-edge trigger
[1] Typical values are measured at nominal supply voltage (VCC=3.3 V and VCC=5.0V).
[2] tpd is the same as tPLH and tPHL.
[3] tpd is the same as tPHL only.
[4] CPDis used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs.
trec recovery
time
MR to CP; see Figure8
VCC = 3.0 V to 3.6 V 2.5 - - 2.5 - 2.5 - ns
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - ns
CPD power
dissipation
capacitance=1 MHz; VI= GNDto VCC [4] -14 - - - - - pF
74AHCT273; VCC= 4.5Vto 5.5V
tpd propagation
delayto Qn; see Figure7 [2]=15pF - 4.0 7.5 1.0 8.8 1.0 9.5 ns=50pF - 5.8 9.2 1.0 10.5 1.0 11.5 nsto Qn; see Figure8 [3]=15pF - 3.9 10.0 1.0 11.6 1.0 12.5 ns=50pF - 5.6 11.0 1.0 12.6 1.0 14.0 ns
fmax maximum
frequency
see Figure7=15pF 75 120 - 65 - 65 - MHz=50pF 50 75 - 45 - 45 - MHz pulse width CP HIGH or LOW;
see Figure7
5.0 - - 6.5 - 6.5 - ns
MR LOW; see Figure8 5.0 - - 6.0 - 6.0 - ns
tsu set-up time Dn to CP; see Figure9 3.0 - - 3.0 - 3.0 - ns hold time Dn to CP; see Figure9 1.0 - - 1.0 - 1.0 - ns
trec recovery
time
MR to CP; see Figure8 2.5 - - 2.5 - 2.5 - ns
CPD power
dissipation
capacitance=1 MHz; VI= GNDto VCC [4] -18 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.

Partno	Mfg	Dc	Qty	Available	Descript
74AHC273BQ	NXP	N/a	200	avai	Octal D-type flip-flop with reset; positive-edge trigger
74AHC273PW	NXP	N/a	34000	avai	Octal D-type flip-flop with reset; positive-edge trigger
74AHCT273PW	NXP	N/a	58820	avai	Octal D-type flip-flop with reset; positive-edge trigger