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74AHC1G09GW
2-input AND gate with open-drain output
General descriptionThe 74AHC1G09 is a high-speed Si-gate CMOS device.
The 74AHC1G09 provides the 2-input AND function with open-drain output.
The outputof the 74AHC1G09isan open drain and canbe connectedto other open-drain
outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions. For
digital operation this device must have a pull-up resistor to establish a logic HIGH level.
Features High noise immunity Low power dissipation SOT353-1 and SOT753 package options ESD protection: HBM JESD22-A114E: exceeds 2000V MM JESD22-A115-A: exceeds 200 V CDM JESD22-C101C: exceeds 1000V Specified from −40 °Cto+85 °C and from −40°Cto +125 °C.
Ordering information Marking
74AHC1G09
2-input AND gate with open-drain output
Rev. 02 — 18 December 2007 Product data sheet
Table 1. Ordering information74AHC1G09GW −40 °C to +125°C TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74AHC1G09GV −40 °C to +125°C SC-74A plastic surface-mounted package; 5 leads SOT753
Table 2. Marking74AHC1G09GW A9
74AHC1G09GV A09
NXP Semiconductors 74AHC1G09
2-input AND gate with open-drain output Functional diagram Pinning information
6.1 Pinning
6.2 Pin description Functional description[1]H= HIGH voltage level; L= LOW voltage level; Z = high-impedance OFF-state.
Table 3. Pin description 1 data input B 2 data input A
GND 3 ground (0 V) 4 data output Y
VCC 5 supply voltage
Table 4. Function table[1]LLL L L
HHZ
NXP Semiconductors 74AHC1G09
2-input AND gate with open-drain output Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
Recommended operating conditions
10. Static characteristics
Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage −0.5 +7.0 V input voltage [1] −0.5 +7.0 V output voltage active mode [1] −0.5 +7.0 V
high-impedance mode [1] −0.5 +7.0 V
IIK input clamping current VI< −0.5V [1]- −20 mA
IOK output clamping current VO< −0.5V [1]- ±20 mA output current VO> −0.5V - 25 mA
ICC supply current - ±75 mA
IGND GND current - ±75 mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb= −40°Cto +125°C [2]- 250 mW
Table 6. Recommended operating operationsVCC supply voltage 2.0 5.0 5.5 V input voltage 0 - 5.5 V output voltage active mode 0 - VCC V
high-impedance mode 0 - 6.0 V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC= 3.0Vto 3.6V - - 100 ns/V
VCC= 4.5Vto 5.5V - - 20 ns/V
Table 7. Static characteristicsVoltages are referenced to GND (ground = 0 V).
VIH HIGH-level
input voltage
VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage
VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
NXP Semiconductors 74AHC1G09
2-input AND gate with open-drain output
11. Dynamic characteristics[1] tpd is the same as tPZL and tPLZ.
[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4] CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N +(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;
N = number of inputs switching;
(CL× VCC2× fo) = dissipation due to the output if the combination of the pull up voltage and resistance results in VCC at the output.
VOL LOW-level
output voltage = VIH or VIL = 50 μA; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 3.0 V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V = 4.0 mA; VCC= 3.0 V - - 0.36 - 0.44 - 0.55 V = 8.0 mA; VCC= 4.5 V - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5Vor GND;
VCC=0Vto 5.5V ±0.1 - ±1.0 - ±2.0 μA
IOZ OFF-state
output current = VIH or VIL; VO = VCC or
GND; VCC= 5.5 V ±0.25 ±2.5 ±10.0 μA
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5 V - 1.0 - 10 - 20 μA input
capacitance 1.5 10 - 10 - 10 pF
Table 7. Static characteristics …continuedVoltages are referenced to GND (ground = 0 V).
Table 8. Dynamic characteristicsGND = 0 V; for test circuit see Figure6.
tpd propagation delay A and B toY;
see Figure5
[1]
VCC = 3.0 V to 3.6 V [2]= 15 pF - 4.6 7.5 1.0 8.5 1.0 9.0 ns= 50 pF - 6.5 11.0 1.5 12.0 1.5 12.5 ns
VCC = 4.5 V to 5.5 V [3]= 15 pF - 3.2 5.5 1.0 6.5 1.0 7.0 ns= 50 pF - 4.6 7.5 1.5 8.0 1.5 8.5 ns
CPD power dissipation
capacitance=50 pF;fi=1 MHz;= GNDto VCC
[4] -5- - - - - pF
NXP Semiconductors 74AHC1G09
2-input AND gate with open-drain output
12. Waveforms
Table 9. Measurement points0.5VCC 0.5VCC VOL + 0.3 V
Table 10. Test dataGND to VCC ≤ 3.0 ns 1000Ω 15 pF GND VCC open
GND to VCC ≤ 3.0 ns 1000Ω 50 pF GND VCC open
NXP Semiconductors 74AHC1G09
2-input AND gate with open-drain output
13. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1
