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74AHC1G02GVNXPN/a500avai2-input NOR gate
74AHCT1G02GVNXPN/a18000avai2-input NOR gate


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74AHC1G02GV-74AHCT1G02GV
2-input NOR gate
General description74AHC1G02 and 74AHCT1G02 are high-speed Si-gate CMOS devices. They provide a
2-input NOR function.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. Features Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays SOT353-1 and SOT753 package options ESD protection: HBM JESD22-A114E: exceeds 2000V MM JESD22-A115-A: exceeds 200 V CDM JESD22-C101C: exceeds 1000V Specified from −40°Cto +125°C Ordering information
74AHC1G02; 74AHCT1G02
2-input NOR gate
Rev. 06 — 30 May 2007 Product data sheet
Table 1. Ordering information
74AHC1G02GW −40 °C to +125°C TSSOP5 plastic thin shrink small outline package; leads; body width 1.25 mm
SOT353-1
74AHCT1G02GW
74AHC1G02GV −40 °C to +125°C SC-74A plastic surface-mounted package; 5 leads SOT753
74AHCT1G02GV
NXP Semiconductors 74AHC1G02; 74AHCT1G02
2-input NOR gate Marking Functional diagram Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Marking codes
74AHC1G02GW AB
74AHC1G02GV A02
74AHCT1G02GW CB
74AHCT1G02GV C02
Table 3. Pin description 1 data input B 2 data input A
GND 3 ground (0 V) 4 data output Y
VCC 5 supply voltage
NXP Semiconductors 74AHC1G02; 74AHCT1G02
2-input NOR gate Functional description Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For both TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. Recommended operating conditions
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level
LLH L L
HHL
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VCC supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V −20 - mA
IOK output clamping current VO < −0.5 V or VO >VCC+ 0.5V [1]- ±20 mA output current −0.5 V < VO ICC supply current - 75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40°Cto +125°C [2]- 250 mW
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V input voltage 0 - 5.5 0 - 5.5 V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C
Δt/ΔV input transition rise
and fall rate
VCC = 3.3 V ± 0.3 V - - 100 - - - ns/V
VCC = 5.0 V ± 0.5 V - - 20 - - 20 ns/V
NXP Semiconductors 74AHC1G02; 74AHCT1G02
2-input NOR gate
10. Static characteristics
Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V).
For type 74AHC1G02
VIH HIGH-level
input voltage
VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage
VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage = VIH or VIL= −50 μA; VCC= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V= −50 μA; VCC= 3.0 V 2.9 3.0 - 2.9 - 2.9 - V= −50 μA; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V= −4.0 mA; VCC= 3.0 V 2.58 - - 2.48 - 2.40 - V= −8.0 mA; VCC= 4.5 V 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL = 50 μA; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 3.0 V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V = 4.0 mA; VCC= 3.0 V - - 0.36 - 0.44 - 0.55 V = 8.0 mA; VCC= 4.5 V - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5Vor GND;
VCC=0Vto 5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5 V - 1.0 - 10 - 40 μA input
capacitance 1.5 10 - 10 - 10 pF
For type 74AHCT1G02
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage = VIH or VIL; VCC= 4.5 V= −50μA 4.4 4.5 - 4.4 - 4.4 - V= −8.0 mA 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL; VCC= 4.5 V = 50μA - 0 0.1 - 0.1 - 0.1 V = 8.0 mA - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5Vor GND;
VCC=0Vto 5.5V - 0.1 - 1.0 - 2.0 μA
NXP Semiconductors 74AHC1G02; 74AHCT1G02
2-input NOR gate
11. Dynamic characteristics
[1] tpd is the same as tPLH and tPHL.
[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4] CPD is used to determine the dynamic power dissipation PD (μW). =CPD× VCC2×fi+∑(CL× VCC2×fo) where:= input frequency in MHz; fo= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in Volts.
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5 V - 1.0 - 10 - 40 μA
ΔICC additional
supply current
per input pin; VI= 3.4V;
other inputs at VCCor GND;= 0 A; VCC = 5.5 V - 1.35 - 1.5 - 1.5 mA input
capacitance 1.5 10 - 10 - 10 pF
Table 7. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Table 8. Dynamic characteristics
GND = 0 V; tr = tf = ≤ 3.0 ns. For test circuit see Figure6.
For type 74AHC1G02
tpd propagation
delay
A and B toY;
see Figure5
[1]
VCC = 3.0 V to 3.6 V [2]= 15 pF - 4.4 7.9 1.0 9.5 1.0 10.5 ns= 50 pF - 6.3 11.4 1.0 13 1.0 14.5 ns
VCC = 4.5 V to 5.5 V [3]= 15 pF - 3.2 5.5 1.0 6.5 1.0 7.0 ns= 50 pF - 4.6 7.5 1.0 8.5 1.0 9.5 ns
CPD power
dissipation
capacitance
per buffer;=50 pF;f = 1 MHz;= GNDto VCC
[4] -18- - - - - pF
For type 74AHCT1G02
tpd propagation
delay
A and B toY;
see Figure5
[1]
VCC = 4.5 V to 5.5 V [3]= 15 pF - 3.5 5.5 1.0 6.5 1.0 7.0 ns= 50 pF - 4.9 7.5 1.0 8.5 1.0 9.5 ns
CPD power
dissipation
capacitance
per buffer;=50 pF;f = 1 MHz;= GNDto VCC
[4] -19- - - - - pF
NXP Semiconductors 74AHC1G02; 74AHCT1G02
2-input NOR gate
12. Waveforms
Table 9. Measurement point
74AHC1G02 GND to VCC 0.5 × VCC 0.5 × VCC
74AHCT1G02 GND to 3.0 V 1.5 V 0.5 × VCC
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