74AHC164PW-74AHCT164D Fast Delivery |IC PHOENIX CO.,LIMITED

74AHCT164D ,74AHC164; 74AHCT164; 8-bit serial-in/parallel-out shift registerGeneral descriptionThe 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and i ..
74AHCT1G00DCKRG4 ,Single 2-Input Positive-NAND Gate 5-SC70 -40 to 1256.3 Recommended Operating Conditions(1)over operating free-air temperature range (unless otherwise ..
74AHCT1G00GV ,2-input NAND gateLogic diagram6. Pinning information6.1 Pinning74AHC1G0074AHCT1G00BV 1 5CCA 2GND 3 4 Y001aaf092Fig 4 ..
74AHCT1G00GV ,2-input NAND gate
74AHCT1G00GW ,2-input NAND gateGeneral description74AHC1G00 and 74AHCT1G00 are high-speed Si-gate CMOS devices. They provide a2-in ..
74AHCT1G00SE-7 , SINGLE 2 INPUT POSITIVE NAND GATE
74HC377D ,Octal D-type flip-flop with data enable; positive-edge triggerGENERAL DESCRIPTION• Ideal for addressable register
74HC377DB ,Octal D-type flip-flop with data enable; positive-edge triggerapplicationsstandard no. 7A.• Eight positive-edge triggered D-type flip-flopsThe 74HC/HCT377 have e ..
74HC377N ,74HC/HCT377; Octal D-type flip-flop with data enable; positive-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC377PW ,74HC/HCT377; Octal D-type flip-flop with data enable; positive-edge triggerapplicationsstandard no. 7A.• Eight positive-edge triggered D-type flip-flopsThe 74HC/HCT377 have e ..
74HC377PW ,74HC/HCT377; Octal D-type flip-flop with data enable; positive-edge triggerGeneral descriptionThe 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The ..
74HC390D ,Dual decade ripple counterpin configuration. A HIGH level ondivided into four separately clocked sections. The countersthe nM ..

74AHC164PW-74AHCT164D
8-bit serial-in/parallel-out shift register
General descriptionThe 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is
pin compatible with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with
JEDEC standard No. 7A.
The 74AHC164; 74AHCT164 input signals are 8-bit serial through oneof two inputs (DSA
or DSB); either input can be used as an active HIGH enable for data entry through the
other input. Both inputs must be connected together or an unused input must be tied
HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP)
and enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB)
that existed one set-up time prior to the rising clock edge.
A LOW-level on the master reset (MR) input overrides all other inputs and clears the
register asynchronously, forcing all outputs LOW. Features Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Input levels: For 74AHC164: CMOS level For 74AHCT164: TTL level ESD protection: HBM EIA/JESD22-A114E exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V CDM EIA/JESD22-C101C exceeds 1000V Multiple package options Speciﬁed from −40 °C to +85 °C and from −40 °C to +125°C
74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
Rev. 03 — 24 April 2008 Product data sheet
NXP Semiconductors 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register Ordering information Functional diagram
Table 1. Ordering information
74AHC164
74AHC164D −40 °C to +125°C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74AHC164PW −40 °C to +125°C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74AHC164BQ −40 °C to +125°C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad ﬂat package; no leads; 14 terminals; body
2.5 × 3× 0.85 mm
SOT762-1
74AHCT164
74AHCT164D −40 °C to +125°C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74AHCT164PW −40 °C to +125°C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74AHCT164BQ −40 °C to +125°C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad ﬂat package; no leads; 14 terminals; body
2.5 × 3 × 0.85 mm
SOT762-1
NXP Semiconductors 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
NXP Semiconductors 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
DSA 1 serial data input A
DSB 2 serial data input B 3 output 0 4 output 1 5 output 2 6 output 3
GND 7 ground (0V) 8 clock input (LOW-to-HIGH edge-triggered) 9 master reset input (active LOW) 10 output 4 11 output 5 12 output 6 13 output 7
VCC 14 supply voltage
NXP Semiconductors 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register Functional description
[1]H= HIGH voltage level;= HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;= LOW voltage level;= LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;= LOW-to-HIGH transition;= don’t care;= lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.
Table 3. Function table[1]
Reset (clear) L X X X L L to L
Shift H ↑ l l L q0 to q6 h L q0 to q6 l L q0 to q6 h H q0 to q6
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5V [1] −20 - mA
IOK output clamping current VO < −0.5 V or VO > VCC + 0.5V [1] −20 +20 mA output current VO = −0.5 V to (VCC + 0.5V) −25 +25 mA
ICC supply current - +75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125°C [2]- 500 mW
NXP Semiconductors 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register Recommended operating conditions Static characteristics
Table 5. Operating conditions
74AHC164
VCC supply voltage 2.0 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 3.0 V to 3.6V - - 100 ns/V
VCC = 4.5 V to 5.5V - - 20 ns/V
74AHCT164
VCC supply voltage 4.5 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 4.5 V to 5.5V - - 20 ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
74AHC164
VIH HIGH-level
input voltage
VCC = 2.0V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage
VCC = 2.0V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage = VIH or VIL= −50 μA; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= −50 μA; VCC= 3.0V 2.9 3.0 - 2.9 - 2.9 - V= −50 μA; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= −4.0 mA; VCC= 3.0V 2.58 - - 2.48 - 2.40 - V= −8.0 mA; VCC= 4.5V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL = 50 μA; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 3.0V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V = 4.0 mA; VCC= 3.0V - - 0.36 - 0.44 - 0.55 V = 8.0 mA; VCC= 4.5V - - 0.36 - 0.44 - 0.55 V
NXP Semiconductors 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register input leakage
current= 5.5Vor GND;
VCC =0Vto5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5V - 4.0 - 40 - 80 μA input
capacitance 3 10 - - - - pF
74AHCT164
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage = VIH or VIL; VCC= 4.5 V= −50μA 4.4 4.5 - 4.4 - 4.4 - V= −8.0 mA 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL; VCC= 4.5 V = 50μA - 0 0.1 - 0.1 - 0.1 V = 8.0 mA - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5Vor GND;
VCC =0Vto5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5V - 4.0 - 40 - 80 μA
ΔICC additional
supply current
per input pin; =VCC− 2.1 V; IO= 0 A;
other pinsat VCC or GND;
VCC= 4.5Vto 5.5V - 1.35 - 1.5 - 1.5 mA input
capacitance 3 10 - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
NXP Semiconductors 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
74AHC164
tpd propagation
delayto Qn; see Figure7 [2]
VCC = 3.0 V to 3.6V=15pF - 6.5 12.8 1.0 15.0 1.0 16.0 ns=50pF - 9.3 16.3 1.0 18.5 1.0 20.5 ns
VCC = 4.5 V to 5.5V=15pF - 4.5 9.0 1.0 10.5 1.0 11.5 ns=50pF - 6.4 11.0 1.0 12.5 1.0 14.0 nsto Qn; see Figure8 [3]
VCC = 3.0 V to 3.6V=15pF - 5.3 12.8 1.0 15.0 1.0 16.0 ns=50pF - 7.6 16.3 1.0 18.5 1.0 20.5 ns
VCC = 4.5 V to 5.5V=15pF - 4.0 8.6 1.0 10.0 1.0 11.0 ns=50pF - 5.8 10.6 1.0 12.0 1.0 13.5 ns
fmax maximum
frequency
see Figure7
VCC = 3.0 V to 3.6V=15pF 80 125 - 65 - 50 - MHz=50pF 50 75 - 45 - 35 - MHz
VCC = 4.5 V to 5.5V=15pF 125 175 - 105 - 85 - MHz=50pF 85 115 - 75 - 65 - MHz pulse width CP HIGH or LOW;
see Figure7
VCC = 3.0 V to 3.6V 5.0 - - 5.0 - 5.0 - ns
VCC = 4.5 V to 5.5V 5.0 - - 5.0 - 5.0 - ns
tWL pulse width
LOW
MR; see Figure8
VCC = 3.0 V to 3.6V 5.0 - - 5.0 - 5.0 - ns
VCC = 4.5 V to 5.5V 5.0 - - 5.0 - 5.0 - ns
tsu set-up time DSA, DSB to CP;
see Figure9
VCC = 3.0 V to 3.6V 5.0 - - 6.0 - 6.0 - ns
VCC = 4.5 V to 5.5V 4.5 - - 4.5 - 4.5 - ns hold time DSA, DSB to CP;
see Figure9
VCC = 3.0 V to 3.6V 1.5 - - 1.5 - 1.5 - ns
VCC = 4.5 V to 5.5V 2.0 - - 2.0 - 2.0 - ns
NXP Semiconductors 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0V).
[2] tpd is the same as tPLH and tPHL.
[3] tpd is the same as tPHL only.
[4] CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where: = input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs.
trec recovery
time
MR to CP; see Figure8
VCC = 3.0 V to 3.6V 2.5 - - 2.5 - 2.5 - ns
VCC = 4.5 V to 5.5V 2.5 - - 2.5 - 2.5 - ns
CPD power
dissipation
capacitance
fi = 1 MHz; VI= GNDto VCC [4] -48 - - - - - pF
74AHCT164; VCC = 4.5 V to 5.5V
tpd propagation
delayto Qn; see Figure7 [2]=15pF - 3.4 9.0 1.0 10.5 1.0 11.5 ns=50pF - 4.9 11.0 1.0 12.5 1.0 14.0 nsto Qn; see Figure8 [3]=15pF - 3.5 8.6 1.0 10.0 1.0 11.0 ns=50pF - 5.0 10.6 1.0 12.0 1.0 13.5 ns
fmax maximum
frequency
see Figure7=15pF 125 175 - 105 - 85 - MHz=50pF 85 115 - 75 - 65 - MHz pulse width CP HIGH or LOW;
see Figure7
5.0 - - 5.0 - 5.0 - ns
tWL pulse width
LOW
MR; see Figure8 5.0 - - 5.0 - 5.0 - ns
tsu set-up time DSA, DSB to CP;
see Figure9
4.5 - - 4.5 - 4.5 - ns hold time DSA, DSB to CP;
see Figure9
2.0 - - 2.0 - 2.0 - ns
trec recovery
time
MR to CP; see Figure8 2.5 - - 2.5 - 2.5 - ns
CPD power
dissipation
capacitance
fi = 1 MHz; VI= GNDto VCC [4] -51 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.

Partno	Mfg	Dc	Qty	Available	Descript
74AHC164PW	NXP	N/a	30000	avai	8-bit serial-in/parallel-out shift register
74AHCT164D	NXP	N/a	78500	avai	74AHC164; 74AHCT164; 8-bit serial-in/parallel-out shift register