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74AHC157D-74AHCT157D-74AHCT157PW
Quad 2-input multiplexer
Philips Semiconductors Product specification
Quad 2-input multiplexer 74AHC157;
74AHCT157
FEATURES ESD protection: HBM EIA/JESD22-A114-A
exceeds 2000 V MM EIA/JESD22-A115-A
exceeds 200 V CDM EIA/JESD22-C101
exceeds 1000V Balanced propagation delays All inputs have Schmitt-trigger actions Multiple input enable for easy expansion Ideal for memory chip select decoding Inputs accept voltages higher than VCC For AHC only: operates with CMOS input levels For AHCT only: operates with TTL input levels Specified from −40to +85 and +125 °C.
FUNCTION TABLESee note1.
Note H= HIGH voltage level;= LOW voltage level;= don’t care.
DESCRIPTIONThe 74AHC/AHCT157 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT157are quad2-input multiplexers which
select4 bitsof data from two sources under the controlof
a common data select input (S). The enable input (E) is
active LOW. WhenEis HIGH,allof the outputs (1Yto 4Y)
are forced LOW regardless of all other input conditions.
Moving the data from two groups of registers to four
common output buses is a common use of the ‘157’. The
state of the common data select input (S) determines the
particular register from which the data comes. It can also
be used as a function generator.
The deviceis usefulfor implementing highly irregular logic generating any fourof the16 different functionsof two
variables with one variable common.
The ‘157’is the logic implementation ofa 4-pole, 2-position
switch, where the positionof the switchis determineby the
logic levels applied toS.
The logic equations are:=E× (1I1× S+1I0× S);=E× (2I1× S+2I0× S);=E× (3I1× S+3I0× S);=E× (4I1× S+4I0× S).
The ‘157’ is identical to the ‘158’ but has non-inverting
(true) outputs.
ORDERING INFORMATION
Philips Semiconductors Product specification
Quad 2-input multiplexer 74AHC157;
74AHCT157
QUICK REFERENCE DATAGND=0 V; Tamb =25 °C; tr =tf≤ 3.0 ns.
Notes CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi+∑ (CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz; (CL× VCC2×fo)= sum of outputs;= output load capacitance in pF;
VCC= supply voltage in Volts. The condition is VI= GNDto VCC.
PINNING
Philips Semiconductors Product specification
Quad 2-input multiplexer 74AHC157;
74AHCT157
Philips Semiconductors Product specification
Quad 2-input multiplexer 74AHC157;
74AHCT157
Philips Semiconductors Product specification
Quad 2-input multiplexer 74AHC157;
74AHCT157
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground=0V).
Notes The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
Philips Semiconductors Product specification
Quad 2-input multiplexer 74AHC157;
74AHCT157
DC CHARACTERISTICS
74AHC familyOver recommended operating conditions; voltage are referenced to GND (ground=0 V).
Philips Semiconductors Product specification
Quad 2-input multiplexer 74AHC157;
74AHCT157
74AHCT familyOver recommended operating conditions; voltage are referenced to GND (ground=0 V).
