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74AHC139PW
Dual 2-to-4 line decoder/demultiplexer
General descriptionThe 74AHC139; 74AHCT139isa high-speed Si-gate CMOS device andis pin compatible
with Low-power Schottky TTL (LSTTL).Itis specifiedin compliance with JEDEC standard
No. 7-A.
The 74AHC139; 74AHCT139isa high-speed, dual 2-to-4 line decoder/demultiplexer. This
device has two independent decoders, each accepting two binary weighted inputs (nA0
and nA1) and providing four mutually exclusive active LOW outputs (nY0to nY3). Each
decoder has an active LOW enable input (nE). When nE is HIGH, every output is forced
HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer
application.
The 74AHC139; 74AHCT139 is identical to the HEF4556 of the HE4000B family.
Features Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Input levels: For 74AHC139: CMOS level For 74AHCT139: TTL level ESD protection: HBM EIA/JESD22-A114E exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V CDM EIA/JESD22-C101C exceeds 1000V Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125°C
Ordering information
74AHC139; 74AHCT139
Dual 2-to-4 line decoder/demultiplexer
Rev. 02 — 9 May 2008 Product data sheet
Table 1. Ordering information
74AHC13974AHC139D −40 °C to +125°C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74AHC139PW −40 °C to +125°C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
NXP Semiconductors 74AHC139; 74AHCT139
Dual 2-to-4 line decoder/demultiplexer Functional diagram
74AHCT13974AHCT139D −40 °C to +125°C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74AHCT139PW −40 °C to +125°C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
Table 1. Ordering information …continued
NXP Semiconductors 74AHC139; 74AHCT139
Dual 2-to-4 line decoder/demultiplexer Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 enable input (active LOW)
1A0 2 address input
1A1 3 address input
1Y0 4 output
1Y1 5 output
1Y2 6 output
1Y3 7 output
GND 8 ground (0V)
2Y3 9 output
2Y2 10 output
2Y1 11 output
2Y0 12 output
2A1 13 address input
2A0 14 address input 15 enable input (active LOW)
VCC 16 supply voltage
NXP Semiconductors 74AHC139; 74AHCT139
Dual 2-to-4 line decoder/demultiplexer Functional description[1]H= HIGH voltage level;= LOW voltage level;= don’t care.
Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
Table 3. Function table[1] X X HHHH L L L HHH L HL HH H HHL H H HHHL
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5V [1] −20 - mA
IOK output clamping current VO < −0.5 V or VO > VCC + 0.5V [1] −20 +20 mA output current VO = −0.5 V to (VCC + 0.5V) −25 +25 mA
ICC supply current - +75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb= −40°Cto +125°C [2]- 500 mW
NXP Semiconductors 74AHC139; 74AHCT139
Dual 2-to-4 line decoder/demultiplexer Recommended operating conditions Static characteristics
Table 5. Operating conditions
74AHC139VCC supply voltage 2.0 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC= 3.0Vto 3.6V - - 100 ns/V
VCC= 4.5Vto 5.5V - - 20 ns/V
74AHCT139VCC supply voltage 4.5 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC= 4.5Vto 5.5V - - 20 ns/V
Table 6. Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground = 0V).
74AHC139VIH HIGH-level
input voltage
VCC= 2.0V 1.5 - - 1.5 - 1.5 - V
VCC= 3.0V 2.1 - - 2.1 - 2.1 - V
VCC= 5.5V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage
VCC= 2.0V - - 0.5 - 0.5 - 0.5 V
VCC= 3.0V - - 0.9 - 0.9 - 0.9 V
VCC= 5.5V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage =VIHorVIL= −50 μA; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= −50 μA; VCC= 3.0V 2.9 3.0 - 2.9 - 2.9 - V= −50 μA; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= −4.0 mA; VCC= 3.0V 2.58 - - 2.48 - 2.40 - V= −8.0 mA; VCC= 4.5V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage =VIHorVIL =50 μA; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =50 μA; VCC= 3.0V - 0 0.1 - 0.1 - 0.1 V =50 μA; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V= 4.0 mA; VCC= 3.0V - - 0.36 - 0.44 - 0.55 V= 8.0 mA; VCC= 4.5V - - 0.36 - 0.44 - 0.55 V
NXP Semiconductors 74AHC139; 74AHCT139
Dual 2-to-4 line decoder/demultiplexer input leakage
current= 5.5Vor GND;
VCC=0Vto 5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply current VI =VCCor GND; IO =0A;
VCC= 5.5V - 4.0 - 40 - 80 μA input
capacitance =VCCor GND - 3 10 - 10 - 10 pF output
capacitance 4 - - --- pF
74AHCT139VIH HIGH-level
input voltage
VCC = 4.5Vto 5.5V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5Vto 5.5V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC= 4.5V= −50μA 4.4 4.5 - 4.4 - 4.4 - V= −8.0 mA 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage =VIHor VIL; VCC= 4.5V =50μA - 0 0.1 - 0.1 - 0.1 V= 8.0 mA - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5Vor GND;
VCC=0Vto 5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply current VI =VCCor GND; IO =0A;
VCC= 5.5V - 4.0 - 40 - 80 μA
ΔICC additional
supply current
per input pin; =VCC− 2.1 V; other pins
at VCCor GND; IO =0A;
VCC= 4.5Vto 5.5V - 1.35 - 1.5 - 1.5 mA input
capacitance =VCCor GND - 3 10 - 10 - 10 pF output
capacitance 4 - - --- pF
Table 6. Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground = 0V).
NXP Semiconductors 74AHC139; 74AHCT139
Dual 2-to-4 line decoder/demultiplexer
10. Dynamic characteristics[1] Typical values are measured at nominal supply voltage (VCC=3.3 V and VCC=5.0V).
[2] tpd is the same as tPLH and tPHL.
[3] CPDis used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs.
Table 7. Dynamic characteristicsVoltages are referenced to GND (ground = 0 V); for test circuit see Figure7.
74AHC139tpd propagation
delay
nAnto nYn; see Figure5 [2]
VCC= 3.0Vto 3.6V=15pF - 5.5 11.0 1.0 13.0 1.0 14.0 ns=50pF - 7.9 14.5 1.0 16.5 1.0 18.5 ns
VCC= 4.5Vto 5.5V=15pF - 3.9 7.2 1.0 8.5 1.0 9.0 ns=50pF - 5.6 9.2 1.0 10.5 1.0 11.5 ns
nEtonYn; see Figure6 [2]
VCC= 3.0Vto 3.6V=15pF - 4.8 9.2 1.0 11.0 1.0 11.5 ns=50pF - 6.9 12.7 1.0 14.5 1.0 16.0 ns
VCC= 4.5Vto 5.5V=15pF - 3.4 6.3 1.0 7.5 1.0 8.0 ns=50pF - 4.9 8.3 1.0 9.5 1.0 10.5 ns
CPD power
dissipation
capacitance=1 MHz; VI= GNDto VCC [3] -26 - - - - - pF
74AHCT139; VCC= 4.5Vto 5.5Vtpd propagation
delay
nAnto nYn; see Figure5 [2]=15pF - 4.7 7.2 1.0 8.5 1.0 9.0 ns=50pF - 6.5 9.2 1.0 10.5 1.0 11.5 ns
nEtonYn; see Figure6 [2]=15pF - 3.6 6.3 1.0 7.5 1.0 8.0 ns=50pF - 5.2 8.3 1.0 9.5 1.0 10.5 ns
CPD power
dissipation
capacitance=1 MHz; VI= GNDto VCC [3] -23 - - - - - pF