74ACTQ273SJX ,Quiet Series Octal D Flip-FlopFeaturesThe ACTQ273 has eight edge-triggered D-type flip-flops
74ACTQ273PC-74ACTQ273SJ-74ACTQ273SJX
Quiet Series Octal D Flip-Flop
74ACTQ273 Quiet Series Octal D-Type Flip-Flop August 1989 Revised August 2001 74ACTQ273 Quiet Series Octal D-Type Flip-Flop General Description Features The ACTQ273 has eight edge-triggered D-type flip-flopsI reduced by 50% CC with individual D inputs and Q outputs. The common buff- Guaranteed simultaneous switching noise level and ered Clock (CP) and Master Reset (MR) input load and dynamic threshold performance reset (clear) all flip-flops simultaneously. Guaranteed pin-to-pin skew AC performance The register is fully edge-triggered. The state of each D- Improved latch-up immunity type input, one setup time before the LOW-to-HIGH clock Buffered common clock and asynchronous master reset transition, is transferred to the corresponding flip-flop’s Q output.Outputs source/sink 24 mA All outputs will be forced LOW independently of Clock or4 kV minimum ESD immunity Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The ACTQ utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance. Ordering Code: Order Number Package Number Package Description 74ACTQ273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACTQ273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACTQ273PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description D –D Data Inputs 0 7 MR Master Reset CP Clock Pulse Input Q –Q Data Outputs 0 7 FACT, FACT Quiet Series, and GTO are trademarks of . © 2001 DS010585
