74ACTQ240 ,Quiet Series Octal Buffer/Line Driver with 3-STATE OutputsFeaturesThe ACQ/ACTQ240 is an inverting octal buffer and line
74ACTQ240
Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs
74ACQ240 • 74ACTQ240 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs July 1989 Revised October 2000 74ACQ240 74ACTQ240 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The ACQ/ACTQ240 is an inverting octal buffer and lineI and I reduced by 50% CC OZ driver designed to be employed as a memory address Guaranteed simultaneous switching noise level and driver, clock driver and bus oriented transmitter or receiver dynamic threshold performance which provides improved PC board density. The ACQ/ Guaranteed pin-to-pin skew AC performance ACTQ utilizes Fairchild’s Quiet Series technology to Improved latch-up immunity guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series featuresInverting 3-STATE outputs drive bus lines or buffer GTO output control and undershoot corrector in addition memory address registers to a split ground bus for superior performance. Outputs source/sink 24 mA Faster prop delays than the standard ACT240 Ordering Code: Order Number Package Number Package Description 74ACQ240SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACQ240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACQ240PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACTQ240SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACTQ240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ240QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide 74ACTQ240PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description OE , OE 3-STATE Output Enable Inputs 1 2 I –I Inputs 0 7 O –O Outputs 0 7 FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of . © 2000 DS010234
