74ACTQ18823 ,18-Bit D-Type Flip-Flop with 3-STATE Outputsapplications. The device is byte controlled. A buff-
74ACTQ18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
74ACTQ18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs September 1991 Revised November 1999 74ACTQ18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs General Description Features The ACTQ18823 contains eighteen non-inverting D-typeUtilizes Fairchild’s FACT Quiet Series technology flip-flops with 3-STATE outputs and is intended for bus ori-Broadside pinout allows for easy board layout ented applications. The device is byte controlled. A buff- Guaranteed simultaneous switching noise level and ered clock (CP), Clear (CLR), Clock Enable (EN) and dynamic threshold performance Output Enable (OE) are common to each byte and can be Guaranteed pin-to-pin output skew shorted together for full 18-bit operation. The ACTQ18823 utilizes Fairchild’s Quiet Series technol-Separate control logic for each byte ogy to guarantee quiet output switching and improvedExtra data width for wider address/data paths or buses dynamic threshold performance. FACT Quiet Series fea- carrying parity tures GTO output control and undershoot corrector for Outputs source/sink 24 mA superior performance. Additional specs for Multiple Output Switching Output loading specs for both 50 pF and 250 pF loads Ordering Code: Order Number Package Number Package Description 74ACTQ18823SSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ACTQ18823MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) n CLR Clear (Active LOW) n EN Clock Enable (Active LOW) n CP Clock Pulse Input n I –I Inputs 0 17 O –O Outputs 0 17 FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of . © 1999 DS010953
