74ACTQ16240 ,16-Bit Inverting Buffer/Line Driver with 3-STATE OutputsFeaturesThe ACTQ16240 contains sixteen inverting buffers with 3- Utilizes Fairchild’s FACT Quiet S ..
74ACTQ16240 ,16-Bit Inverting Buffer/Line Driver with 3-STATE OutputsFeaturesYUtilizes NSC FACT Quiet Series technologyThe ’ACTQ16240 contains sixteen inverting buffers ..
74ACTQ16240 ,16-Bit Inverting Buffer/Line Driver with 3-STATE OutputsFunctional DescriptionThe ACTQ16240 contains sixteen inverting buffers with 3-Inputs OutputsSTATE s ..
74ACTQ16244 ,16-Bit Buffer/Line Driver with TRI-STATE Outputs
74ACTQ16244 ,16-Bit Buffer/Line Driver with TRI-STATE OutputsFeaturesYUtilizes NSC FACT Quiet Series technologyThe ’ACTQ16244 contains sixteen non-inverting buf ..
74ACTQ16244SSC ,16-Bit Buffer/Line Driver with 3-STATE OutputsFunctional DescriptionThe ACTQ16244 contains sixteen non-inverting bufferswith 3-STATE standard out ..
74HC259N ,8-bit addressable latchPin configuration (DIP16, SO16, SSOP16 and Fig 5.
74HC259PW ,74HC/HCT259; 8-bit addressable latchapplications should only be done while in the memory mode. The modein digital systems. The “259” ar ..
74HC273BQ ,Octal D-type flip-flop with reset; positive-edge triggerGENERAL DESCRIPTION• Ideal buffer for MOS microprocessor or memory The 74HC/HCT273 are high-speed S ..
74HC273D ,Octal D-type flip-flop with reset; positive-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC273DB ,Octal D-type flip-flop with reset; positive-edge triggerFeatures and benefits Input levels: For 74HC273: CMOS level For 74HCT273: TTL level Common cloc ..
74HC273N ,74HC/HCT273; Octal D-type flip-flop with reset; positive-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74ACTQ16240
16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
74ACTQ16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs May 1991 Revised November 1998 74ACTQ16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs General Description Features The ACTQ16240 contains sixteen inverting buffers with 3- � Utilizes Fairchild’s FACT Quiet Series technology STATE outputs designed to be employed as a memory and � Guaranteed simultaneous switching noise level and address driver, clock driver, or bus-oriented transmitter/ dynamic threshold performance receiver. The device is nibble controlled. Each nibble has � Guaranteed pin-to-pin output skew separate 3-STATE control inputs which can be shorted � Separate control logic for each byte together for full 16-bit operation. The ACTQ16240 utilizes Fairchild’s Quiet Series technol- � 16-bit version of the ACTQ240 ogy to guarantee quiet output switching and improve � Outputs source/sink 24 mA dynamic threshold performance. FACT Quiet Series fea- � Additional specs for multiple output switching tures GTO output control for superior performance. � Output loading specs for both 50 pF and 250 pF loads Ordering Code: Order Number Package Number Package Description 74ACTQ16240SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ACTQ16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Assignment for SSOP and TSSOP Pin Descriptions Pin Names Description OE Output Enable Inputs (Active Low) n I –I Inputs 0 15 O –O Outputs 0 15 FACT, FACT Quiet Series, Quiet Series, and GTO are trademarks of . © 1999 DS010924.prf
