74ACT715SCX ,Programmable Video Sync GeneratorFeaturesEqualization and serration pulses can be introduced into Maximum Input Clock Frequency > 13 ..
74ACT74 ,DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR74ACT74DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR ■ HIGH SPEED: f = 250MHz (TYP.) at V = 5VMAX CC ..
74ACT74B ,DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEARlogic diagram has not be used to estimate propagation delays2/1274ACT74
74ACT74M ,DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEARAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74ACT74MTC ,Dual D-Type Positive Edge-Triggered Flip-Flop74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-FlopNovember 1988Revised February 200574A ..
74ACT74MTCX ,Dual D-Type Positive Edge-Triggered Flip-Flop74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-FlopNovember 1988Revised February 200574A ..
74HC245N ,74HC/HCT245; Octal bus transceiver; 3-stateGeneral descriptionThe 74HC245; 74HCT245 is a high-speed Si-gate CMOS device and is pin compatiblew ..
74HC245PW ,Octal bus transceiver; 3-stateGeneral descriptionThe 74HC245; 74HCT245 is a high-speed Si-gate CMOS device and is pin compatiblew ..
74HC251 ,3-state
74HC251 ,3-state
74HC251 ,3-state
74HC251D ,8-input multiplexer; 3-stateLogic diagram74HC_HCT251 All information provided in this document is subject to legal disclaimers. ..
74ACT715PC-74ACT715SCX
Programmable Video Sync Generator
74ACT715•74ACT715-R Programmable Video Sync Generator November 1988 Revised December 1998 74ACT715•74ACT715-R Programmable Video Sync Generator to a Clock Enabled state. Bit 10 of the Status Register General Description defaults to a logic “1”. Although completely (re)programma- The ACT715 and ACT715-R are 20-pin TTL-input compati- ble, the ACT715-R version is better suited for applications ble devices capable of generating Horizontal, Vertical and using the default 14.31818 MHz RS-170 register values. Composite Sync and Blank signals for televisions and This feature allows power-up directly into operation, follow- monitors. All pulse widths are completely definable by the ing a single CLEAR pulse. user. The devices are capable of generating signals for both interlaced and noninterlaced modes of operation. Features Equalization and serration pulses can be introduced into � Maximum Input Clock Frequency > 130 MHz the Composite Sync signal when needed. Four additional signals can also be made available when � Interlaced and non-interlaced formats available Composite Sync or Blank are used. These signals can be � Separate or composite horizontal and vertical Sync and used to generate horizontal or vertical gating pulses, cursor Blank signals available position or vertical Interrupt signal. � Complete control of pulse width via register These devices make no assumptions concerning the sys- programming tem architecture. Line rate and field/frame rate are all a � All inputs are TTL compatible function of the values programmed into the data registers, � 8 mA drive on all outputs the status register, and the input clock frequency. � Default RS170/NTSC values mask programmed into The ACT715 is mask programmed to default to a Clock registers Disable state. Bit 10 of the Status Register, Register 0, defaults to a logic “0”. This facilitates (re)programming � ACT715-R is mask programmed to default to a Clock before operation. Enable state for easier start-up into 14.31818MHz RS170 timing The ACT715-R is the same as the ACT715 in all respects except that the ACT715-R is mask programmed to default Ordering Code: Order Number Package Number Package Description 74ACT715SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74ACT715PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT715-RSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74ACT715-RPC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Assignment for DIP and SOIC FACT is a trademark of . © 1999 DS010137.prf
