74ACT646SPC , Octal Bus Transceiver/Register with 3-STATE Outputs74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE OutputsNovember 1988Revised December 199 ..
74ACT652 ,Transceiver/RegisterFeaturesThe ACT652 consists of bus transceiver circuits with D-
74ACT646SPC
Octal Bus Transceiver/Register with 3-STATE Outputs
74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE Outputs November 1988 Revised December 1998 74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE Outputs General Description Features The AC/ACT646 consist of registered bus transceiver cir- � Independent registers for A and B buses cuits, with outputs, D-type flip-flops and control circuitry � Multiplexed real-time and stored data transfers providing multiplexed transmission of data directly from the � 3-STATE outputs input bus or from the internal storage registers. Data on the � 300 mil dual-in-line package A or B bus will be loaded into the respective registers on � Outputs source/sink 24 mA the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental data handling � ACT646 has TTL compatible inputs functions available are illustrated in Figure 1, Figure 2, Fig- ure 3, and Figure 4. Ordering Code: Order Number Package Number Package Description 74AC646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74AC646SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide 74ACT646SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram Pin Assignment for DIP and SOIC IEEE/IEC Pin Descriptions Pin Names Description A –A Data Register A Inputs 0 7 Data Register A Outputs B –B Data Register B Inputs 0 7 Data Register B Outputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Transmit/Receive Inputs Output Enable Input G DIR Direction Control Input FACT is a trademark of . © 1999 DS010132.prf
