74ACT573B ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT NON INVERTINGAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74ACT573B ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT NON INVERTINGLOGIC DIAGRAM This
74ACT573M ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT NON INVERTINGlogic diagram has not be used to estimate propagation delays2/1174ACT573
74ACT573M ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT NON INVERTING74ACT573OCTAL D-TYPE LATCHWITH 3 STATE OUTPUTS (NON INVERTED) ■ HIGH SPEED: t = 5ns (TYP.) at V = ..
74ACT573MTC ,Octal Latch with 3-STATE Outputs74AC573 • 74ACT573 Octal Latch with 3-STATE OutputsNovember 1988Revised March 200574AC573 74ACT57 ..
74ACT573MTCX ,Octal Latch with 3-STATE Outputs74AC573 • 74ACT573 Octal Latch with 3-STATE OutputsNovember 1988Revised March 200574AC573 74ACT57 ..
74HC245D ,74HC/HCT245; Octal bus transceiver; 3-stateGeneral descriptionThe 74HC245; 74HCT245 is a high-speed Si-gate CMOS device and is pin compatiblew ..
74HC245DB ,74HC/HCT245; Octal bus transceiver; 3-stateGeneral descriptionThe 74HC245; 74HCT245 is a high-speed Si-gate CMOS device and is pin compatiblew ..
74HC245N ,74HC/HCT245; Octal bus transceiver; 3-stateGeneral descriptionThe 74HC245; 74HCT245 is a high-speed Si-gate CMOS device and is pin compatiblew ..
74HC245PW ,Octal bus transceiver; 3-stateGeneral descriptionThe 74HC245; 74HCT245 is a high-speed Si-gate CMOS device and is pin compatiblew ..
74HC251 ,3-state
74HC251 ,3-state
74ACT573B-74ACT573M-74ACT573MTR
OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT NON INVERTING
1/11April 2001 HIGH SPEED: tPD = 5ns (TYP .) at VCC = 5V LOW POWER DISSIPATION:
ICC = 4μA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTSIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74ACT573 is an advanced high-speed CMOS
OCTAL D-TYPE LATCH with 3 STATE OUTPUT
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2 MOS
technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input .
When the LE is taken low, the Q outputs will be
latched precisely or inversely at the logic level of D
input data. While the (OE) input is low, the 8
outputs will be in a normal logic state (high or low
logic level) and while high level the outputs will be
in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT573OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS (NON INVERTED)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74ACT5732/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t care
Z : High Impedance
NOTE: Outputs are latched at the time when the input is taken LOW logic level
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
74ACT5733/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 0.8V to 2.0V
74ACT5734/11
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) (*) Voltage range is 5.0V ± 0.5V
74ACT5735/11
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74ACT5736/11
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH,
Dn to LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
