74ACT533 ,Octal Transparent Latch with 3-STATE OutputsFunctional Description Truth TableThe ACT533 contains eight D-type latches with 3-STATE Inputs Outp ..
74ACT534 ,Octal D Flip-Flop with TRI-STATE OutputsFeaturesYI and I reduced by 50%The ’ACT534 is a high-speed, low-power octal D-type flip- CC OZYflop ..
74ACT534PC ,Octal D Flip-Flop with 3-STATE OutputsFunctional DescriptionThe ACT534 consists of eight edge-triggered flip-flops with transition. With ..
74ACT534PC ,Octal D Flip-Flop with 3-STATE OutputsFunctional DescriptionThe ACT534 consists of eight edge-triggered flip-flops with transition. With ..
74ACT534SCX ,Octal D Flip-Flop with 3-STATE Outputsapplications. A buffered
74ACT533
Octal Transparent Latch with 3-STATE Outputs
74ACT533 Octal Transparent Latch with 3-STATE Outputs August 1999 Revised October 1999 74ACT533 Octal Transparent Latch with 3-STATE Outputs General Description Features The ACT533 consists of eight latches with 3-STATE out- � I and I reduced by 50% CC OZ puts for bus organized system applications. The flip-flops � Eight latches in a single package appear transparent to the data when Latch Enable (LE) is � 3-STATE outputs drive bus lines or buffer memory HIGH. When LE is low, the data satisfying the input timing address registers requirements is latched. Data appears on the bus when the � Outputs source/sink 24 mA Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. � Inverted version of the ACT373 � TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT533SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ACT533MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT533PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D –D Data Inputs 0 7 LE Latch Enable Input OE Output Enable Input O –O 3-STATE Latch Outputs 0 7 FACT is a trademark of . © 1999 DS500311
