74ACT373MTR ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT NON INVERTINGABSOLUTE MAXIMUM RATINGS Symbol Parameter Value UnitV Supply Voltage -0.5 to +7 VCCV DC Input ..
74ACT373PC ,Octal Transparent Latch with 3-STATE Outputs74AC373 • 74ACT373 Octal Transparent Latch with 3-STATE OutputsNovember 1988Revised March 200574AC3 ..
74ACT373SC ,Octal Transparent Latch with 3-STATE OutputsFunctional DescriptionThe AC/ACT373 contains eight D-type latches with 3-STATE standard outputs. Wh ..
74ACT373SC ,Octal Transparent Latch with 3-STATE OutputsFeaturesThe AC/ACT373 consists of eight latches with 3-STATE
74ACT373B-74ACT373M-74ACT373MTR
OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT NON INVERTING
1/11April 2001 HIGH SPEED: tPD = 6ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:
ICC = 4μA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74ACT373 is a high-speed CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
When the (LE) input is high , the Q outputs follow
the data (D) inputs . When the (LE) is taken low,
the Q outputs will be latched at the logic levels set
up at the D inputs. When the (OE) input is low, the
8 outputs will be in a normal logic state (high or
low logic level); when the (OE) input is high, the
outputs will be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT373OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS (NON INVERTED)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74ACT3732/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t care
Z : High Impedance
NOTE: Outputs are latched at the time when the input is taken LOW logic level
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
74ACT3733/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 0.8V to 2.0V
74ACT3734/11
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on trasmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) (*) Voltage range is 5.0V ± 0.5V
74ACT3735/11
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74ACT3736/11
WAVEFORM 1: PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH, Dn TO LE SETUP AND
HOLD TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
