74ACT138M ,3 TO 8 LINE DECODER (INVERTING)74ACT1383 TO 8 LINE DECODER (INVERTING) ■ HIGH SPEED: t = 5ns (TYP.) at V = 5VPD CC■ LOW POWER DIS ..
74ACT138M ,3 TO 8 LINE DECODER (INVERTING)74ACT1383 TO 8 LINE DECODER (INVERTING) ■ HIGH SPEED: t = 5ns (TYP.) at V = 5VPD CC■ LOW POWER DIS ..
74ACT138M ,3 TO 8 LINE DECODER (INVERTING)LOGIC DIAGRAM This
74ACT138MTR ,3 TO 8 LINE DECODER (INVERTING)logic diagram has not be used to estimate propagation delays2/1074ACT138
74ACT138PC ,1-of-8 Decoder/DemultiplexerFeaturesThe AC/ACT138 is a high-speed 1-of-8 decoder/demulti-
74ACT138B-74ACT138M-74ACT138MTR
3 TO 8 LINE DECODER (INVERTING)
1/10April 2001 HIGH SPEED: tPD = 5ns (TYP .) at VCC = 5V LOW POWER DISSIPATION:CC = 4μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:OH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS:PLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74ACT138 is an advanced high-speed CMOS
3 TO 8 LINE DECODER (INVERTING) fabricated
with sub-micron silicon gate and double-layer
metal wiring C2 MOS tecnology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Three enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT1383 TO 8 LINE DECODER (INVERTING)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74ACT1382/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
74ACT1383/10
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 0.8V to 2.0V
74ACT1384/10
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) (*) Voltage range is 5.0V ± 0.5V
74ACT1385/10
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
74ACT1386/10
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
