74ACT11373DWR ,Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
74ACT11377 ,OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE
74ACT11640NT ,Octal Bus Transceivers 24-PDIP -40 to 85
74ACT11646NT ,Octal Bus Transceivers And Registers 28-PDIP -40 to 85
74ACT125 ,QUAD BUS BUFFER (3-STATE)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74ACT125B ,QUAD BUS BUFFER (3-STATE)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74HC157PW ,74HC/HCT157; Quad 2-input multiplexerGeneral descriptionThe 74HC157; 74HCT157 is a high-speed Si-gate CMOS device and is pin compatible ..
74HC157PW ,74HC/HCT157; Quad 2-input multiplexerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC157PW ,74HC/HCT157; Quad 2-input multiplexer 74HC157; 74HCT157Quad 2-input multiplexerRev. 6 — 27 August 2012 Product data sheet1.
74HC158 ,inverting
74HC158 ,inverting
74HC158N ,Quad 2-input multiplexer; invertingGeneral descriptionThe 74HC is a high-speed Si-gate CMOS device and is pin compatible with low powe ..
74ACT11373-74ACT11373DWR
Octal Transparent D-Type Latches With 3-State Outputs
Inputs Are TTL-Voltage Compatible Flow-Through Architecture OptimizesPCB Layout Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted
CMOS) 1- m Process 500-mA Typical Latch-Up Immunity at
125°C Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, and Standard
Plastic 300-mil DIPs (NT)
descriptionThis 8-bit latch features 3-state outputs designed specifically for driving highly-capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight latches of the 74ACT11373 are transparent D-type latches. While the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When the enable is taken low, the Q outputs are latched at the levels
that were set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impendance third state and increased drive provide the capability to drive
the bus lines in a bus-organized system without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
The 74ACT11373 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each latch)Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
GND
GND
GND
VCCCC
