74ACT11074N ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPWITH CLEAR AND PRESETSCAS498A – DECEMBER 1 ..
74ACT11112DR ,Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC -40 to 85
74ACT11112N ,Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP -40 to 85
74ACT11138 ,3-Line To 8-Line Decoders/Demultiplexers 16-TSSOP -40 to 85
74ACT11151N ,8-Line To 1-Line Data Selectors/Multiplexers 16-PDIP -40 to 85
74ACT11194D ,5 V, 4-bit bidirectional universal shift register
74HC157D ,Quad 2-input multiplexerPin configuration DIP16, SO16, (T)SSOP16 Fig 6.
74HC157N ,Quad 2-input multiplexerLogic diagram Fig 2. logic symbol74HC_HCT157 All information provided in this document is subject t ..
74HC157PW ,74HC/HCT157; Quad 2-input multiplexerGeneral descriptionThe 74HC157; 74HCT157 is a high-speed Si-gate CMOS device and is pin compatible ..
74HC157PW ,74HC/HCT157; Quad 2-input multiplexerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC157PW ,74HC/HCT157; Quad 2-input multiplexer 74HC157; 74HCT157Quad 2-input multiplexerRev. 6 — 27 August 2012 Product data sheet1.
74HC158 ,inverting
74ACT11074-74ACT11074D-74ACT11074N
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
500-mA Typical Latch-Up Immunity 125°C Package Options Include PlasticSmall-Outline (D) and Shrink Small-Outline
(DB) Packages, and Standard Plastic
300-mil DIPs (N)
descriptionThis device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)
or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR
are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs
on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed
without affecting the levels at the outputs.
The 74ACT11074 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE This configuration is unstable; that is, it does not
persist when either PRE or CLR returns to its
inactive (high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
2PRE
1CLR
VCC
2CLR
2CLK
