74ACT10 ,Triple 3-Input NAND Gate74ACT10TRIPLE 3-INPUT NAND GATE ■ HIGH SPEED: t = 4.5ns (TYP.) at V = 5VPD CC■ LOW POWER DISSIPATI ..
74ACT109 ,Dual JK Positive Edge-Triggered Flip-FlopFeaturesThe AC/ACT109 consists of two high-speed completely
74ACT10
Triple 3-Input NAND Gate
1/8April 2001 HIGH SPEED: tPD = 4.5ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 4μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 10 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74ACT10 is an advanced high-speed CMOS
TRIPLE 3-INPUT NAND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C2 MOS tecnology.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
74ACT10TRIPLE 3-INPUT NAND GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74ACT102/8
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 0.8V to 2.0V
74ACT103/8
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on trasmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) (*) Voltage range is 5.0V ± 0.5V
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/3 (per gate)
74ACT104/8
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
