74AC648SPC ,Octal Bus Transceiver/Register with 3-STATE Outputs74AC648 Octal Transceiver/Register with 3-STATE OutputsNovember 1988Revised August 200074AC648Octal ..
74AC74 ,DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOPFeaturesThe AC/ACT74 is a dual D-type flip-flop with Asynchronous * I reduced by 50%CCClear and Set ..
74AC74B ,DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEARLOGIC DIAGRAM This
74AC74M ,DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEARAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74AC74MTCX ,Dual D-Type Positive Edge-Triggered Flip-Flop74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-FlopNovember 1988Revised February 200574A ..
74AC74MTR ,DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEARlogic diagram has not be used to estimate propagation delays2/1274AC74
74HC138BQ ,3-to-8 line decoder, demultiplexer; inverting 74HC138; 74HCT1383-to-8 line decoder/demultiplexer; invertingRev. 4 — 27 June 2012 Product data sh ..
74HC138D ,3-to-8 line decoder, demultiplexer; invertingPin configuration DIP16, SO16, SSOP16 and Fig 5.
74HC138D- ,3-to-8 line decoder, demultiplexer; invertingGENERAL DESCRIPTIONusing one of the active LOW enable inputs as the dataThe 74HC/HCT138 are high-sp ..
74HC138DB ,3-to-8 line decoder, demultiplexer; invertingfeatures three enable inputs: two active LOW(E and E ) and one active HIGH (E ). Every output will ..
74HC138DB ,3-to-8 line decoder, demultiplexer; invertingLogic diagram5. Pinning information5.1 Pinning 74HC138BQ74HCT138BQ74HC13874HCT138terminal 1index ar ..
74HC138N ,74HC/HCT138; 3-to-8 line decoder/demultiplexer; invertingINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74AC648SPC
Octal Bus Transceiver/Register with 3-STATE Outputs
74AC648 Octal Transceiver/Register with 3-STATE Outputs November 1988 Revised August 2000 74AC648 Octal Transceiver/Register with 3-STATE Outputs General Description Features The AC648 consists of registered bus transceiver circuits,Independent registers for A and B buses with outputs, D-type flip-flops and control circuitry providingMultiplexed real-time and stored data transfers multiplexed transmission of data directly from the input bus 3-STATE outputs or from the internal storage registers. Data on the A or B 300 mil slim dual-in-line package bus will be loaded into the respective registers on the Outputs source/sink 24 mA LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental data handling functionsInverted data to output available are illustrated in Figure 1, Figure 2, Figure 3, and Figure 4. Ordering Code: Order Number Package Number Package Description 74AC648SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74AC648SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description A –A Data Register A Inputs, 0 7 Data Register A 3-STATE Outputs B – B Data Register B Inputs, 0 7 Data Register B 3-STATE Outputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Transmit/Receive Inputs DIR, G Output Enable Inputs FACT is a trademark of . © 2000 DS010133
