74AC574TTR ,OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUT NON INVERTINGlogic diagram has not be used to estimate propagation delays2/1174AC574
74AC646 ,Octal Transceiver/Register with 3-STATE Outputs54AC/74AC646 74ACT646#OctalTransceiver/RegisterwithTRI-STATEOutputsMarch199354AC/74AC646 74ACT646#O ..
74AC646 ,Octal Transceiver/Register with 3-STATE Outputs74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE OutputsNovember 1988Revised October 2000 ..
74AC646 ,Octal Transceiver/Register with 3-STATE Outputs74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE OutputsNovember 1988Revised October 2000 ..
74AC646SC ,Octal Bus Transceiver/Register with 3-STATE Outputs74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE OutputsNovember 1988Revised October 2000 ..
74AC646SCX ,Octal Bus Transceiver/Register with 3-STATE Outputs74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE OutputsNovember 1988Revised October 2000 ..
74HC137 ,inverting
74HC137 ,inverting
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74AC574M-74AC574MTR-74AC574TTR
OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUT NON INVERTING
1/11April 2001 HIGH SPEED:
fMAX = 250MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 4μA(MAX.) at TA =25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS:PLH ≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74AC574 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP-FLOP with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2 MOS technology.
These 8 bit D-Type Flip-Flop are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic that were setup at
the D inputs.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level); while
OE is in high level, the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74AC574OCTAL D-TYPE FLIP-FLOP
WITH 3 STATE OUTPUTS (NON INVERTED)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74AC5742/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
Z : High Impedance
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
74AC5743/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 30% to 70% of VCC
74AC5744/11
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
74AC5745/11
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
74AC5746/11
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
