74AC373B ,OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTINGAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74AC373M ,OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING74AC373OCTAL D-TYPE LATCHWITH 3 STATE OUTPUTS (NON INVERTED) ■ HIGH SPEED: t = 5ns (TYP.) at V = 5 ..
74AC373MTC ,Octal Transparent Latch with 3-STATE Outputsapplications. The flip-
74AC373B-74AC373M
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
1/11April 2001 HIGH SPEED: tPD = 5ns (TYP .) at VCC = 5V LOW POWER DISSIPATION:CC = 4μA(MAX.) at TA =25°C HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:OH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS:PLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74AC373 is a high-speed CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2 MOS
technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input. When the LE is
taken low, the Q outputs will be latched at the
logic level of D input data. While the (OE) input is
low, the 8 outputs will be in a normal logic state
(high or low logic level); while OE is in high level
the outputs will be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74AC373OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS (NON INVERTED)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74AC3732/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
Z : High Impedance
NOTE: Outputs are latched at the time when the input is taken LOW logic level
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
74AC3733/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 30% to 70% of VCC
74AC3734/11
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
74AC3735/11
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
74AC3736/11
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES (f=1MHz; 50% duty cycle)
