74AC299M ,8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR74AC2998 BIT PIPO SHIFT REGISTERWITH ASYNCHRONOUS CLEAR ■ HIGH SPEED: ■ f = 240MHz (TYP.) at V = 5 ..
74AC299PC ,8-Input Universal Shift/Storage Register with Common I/O Pins74AC299 • 74ACT299 8-Input Universal Shift/Storage RegisterJuly 1988Revised March 200574AC299 74A ..
74AC299SC ,8-Input Universal Shift/Storage Register with Common I/O PinsFeaturesThe AC/ACT299 is an 8-bit universal shift/storage register
74AC299M
8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR
1/13April 2001 HIGH SPEED: fMAX = 240MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION:
ICC = 8μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 299 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74AC299 is an advanced high-speed CMOS
8-BIT PIPO SHIFT REGISTER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS technology.
These devices have four modes (HOLD, SHIFT
LEFT, SHIFT RIGHT and LOAD DATA). Each
mode is chosen by two function select inputs (S0,
S1) as shown in the Truth Table. When one or
both enable inputs, (G1, G2) are high, the eight
input/output terminals are in the high-impedance
state; however sequential operation or clearing of
the register is not affected. Clear function is
asynchronous to clock.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74AC2998 BIT PIPO SHIFT REGISTER
WITH ASYNCHRONOUS CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74AC2992/13
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE * When one or both controls are high, the eight input/output terminals are the high impedance state: howewer sequential operation or cleaning
of the register is not affected.
Z : High Impedance
Qn0 : The level of An before the indicated steady state input conditions were established.
Qnn : The level of Qn before the most recent active transition indicated by OR
a, h : The level of the steadystate inputs A, H, respectively.
X : Don’t Care
74AC2993/13
LOGIC DIAGRAM
74AC2994/13
TIMING CHART
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 30% to 70% of VCC
74AC2995/13
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
74AC2996/13
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
74AC2997/13
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
