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Home ›  774 > 74AC273MTC-74AC273MTCX-74AC273PC-74AC273SC-74AC273SCX-74AC273SJ-74AC273SJX-74ACT273MTC-74ACT273MTCX-74ACT273SCX,Octal D-Type Flip-Flop
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74AC273MTCFSCN/a100avaiOctal D-Type Flip-Flop
74AC273MTCFAIN/a1365avaiOctal D-Type Flip-Flop
74AC273MTCXFSCN/a366avaiOctal D-Type Flip-Flop
74AC273PCFSC.N/a15avaiOctal D-Type Flip-Flop
74AC273SCFSCN/a65avaiOctal D-Type Flip-Flop
74AC273SCXFAIR/PBFN/a19715avaiOctal D-Type Flip-Flop
74AC273SJFAIN/a40avaiOctal D-Type Flip-Flop
74AC273SJfai Pb-freeN/a1202avaiOctal D-Type Flip-Flop
74AC273SJXNSN/a1950avaiOctal D-Type Flip-Flop
74AC273SJXN/a3980avaiOctal D-Type Flip-Flop
74ACT273MTCFAIN/a670avaiOctal D-Type Flip-Flop
74ACT273MTCXFairchild ?N/a1100avaiOctal D-Type Flip-Flop
74ACT273MTCXFSCN/a2500avaiOctal D-Type Flip-Flop
74ACT273MTCXFAIRCHILDN/a1830avaiOctal D-Type Flip-Flop
74ACT273SCXFAIRCHILN/a36avaiOctal D-Type Flip-Flop
74ACT273SCXFAIN/a170avaiOctal D-Type Flip-Flop


74AC273SCX ,Octal D-Type Flip-Flop74AC273 • 74ACT273 Octal D-Type Flip-FlopNovember 1988Revised March 200574AC273  74ACT273Octal D-T ..
74AC273SJ ,Octal D-Type Flip-Flopapplications where the true output onlyis required and the Clock and Master Reset are common toall ..
74AC273SJ ,Octal D-Type Flip-FlopFeaturesThe AC273 and ACT273 have eight edge-triggered D-type

74AC273MTC-74AC273MTCX-74AC273PC-74AC273SC-74AC273SCX-74AC273SJ-74AC273SJX-74ACT273MTC-74ACT273MTCX-74ACT273SCX
Octal D-Type Flip-Flop
74AC273 • 74ACT273 Octal D-Type Flip-Flop November 1988 Revised March 2005 74AC273  74ACT273 Octal D-Type Flip-Flop General Description Features The AC273 and ACT273 have eight edge-triggered D-typeIdeal buffer for microprocessor or memory flip-flops with individual D-type inputs and Q outputs. TheEight edge-triggered D-type flip-flops common buffered Clock (CP) and Master Reset (MR) input Buffered common clock load and reset (clear) all flip-flops simultaneously. Buffered, asynchronous master reset The register is fully edge-triggered. The state of each D- See 377 for clock enable version type input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s QSee 373 for transparent latch version output.See 374 for 3-STATE version All outputs will be forced LOW independently of Clock orOutputs source/sink 24 mA Data inputs by a LOW voltage level on the MR input. The 74ACT273 has TTL-compatible inputs device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Ordering Code: Package Order Number Package Description Number 74AC273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74AC273SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC273PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACT273SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT273MTCX_NL MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide 74ACT273PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. FACT¥ is a trademark of . © 2005 DS009954
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