74AC273B ,OCTAL D-TYPE FLIP FLOP WITH CLEARAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74AC273M ,OCTAL D-TYPE FLIP FLOP WITH CLEAR74AC273OCTAL D-TYPE FLIP FLOP WITH CLEAR ■ HIGH SPEED: ■ f = 250MHz (TYP.) at V = 5VMAX CC■ LOW PO ..
74AC273MTC ,Octal D-Type Flip-Flop74AC273 • 74ACT273 Octal D-Type Flip-FlopNovember 1988Revised March 200574AC273 74ACT273Octal D-T ..
74AC273MTC ,Octal D-Type Flip-FlopFeaturesThe AC273 and ACT273 have eight edge-triggered D-type
74AC273B-74AC273M
OCTAL D-TYPE FLIP FLOP WITH CLEAR
1/11April 2001 HIGH SPEED: fMAX = 250MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION:
ICC = 8μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74AC273 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP WITH CLEAR
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS technology.
Information signals applied to D inputs are
transfered to the Q output on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentely of the other inputs.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74AC273OCTAL D-TYPE FLIP FLOP WITH CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74AC2732/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
74AC2733/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 30% to 70% of VCC
74AC2734/11
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
74AC2735/11
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit)
74AC2736/11
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
