MC74ACT175D ,Quad D Flip-Flop With Master ResetLOGIC DIAGRAMMR CP D D D D3 2 1 0D Q D Q D Q D QCP Q CP Q CP Q CP QCD CD CD CDQ Q Q Q Q Q Q Q3 3 2 ..
MC74ACT175DR2 ,Quad D Flip-Flop With Master ResetMAXIMUM RATINGS*Symbol Parameter Value UnitV DC Supply Voltage (Referenced to GND) –0.5 to +7.0 VCC ..
MC74ACT175N ,Quad D Flip-Flop With Master Reset** * * QUAD D FLIP-FLOP WITH MASTER RESET **The MC74AC/ACT175 is a high-speed quad D flip-flop. Th ..
MC74ACT20D ,DUAL 4-INPUT NAND GATEMAXIMUM RATINGS*Symbol Parameter Value UnitV DC Supply Voltage (Referenced to GND) –0.5 to +7.0 VCC ..
MC74ACT20DR2 ,Dual 4-Input NAND GateMAXIMUM RATINGS*MC74AC20N PDIP–14 25 Units/RailRating Symbol Value UnitMC74ACT20N PDIP–14 25 Units/ ..
MC74ACT240 ,Octal Buffer/Line Driver with 3-State Outputs3MC74AC240, MC74ACT240AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semic ..
MCP2551 , High-Speed CAN Transceiver
MCP3010 , NON-ZERO-CROSSING TRIACS
MCP3010 , NON-ZERO-CROSSING TRIACS
MCP3010 , NON-ZERO-CROSSING TRIACS
MCP6002-I/MS , 1 MHz Bandwidth Low Power Op Amp
MCP6002I/SN , 1 MHz Bandwidth Low Power Op Amp
74AC175-MC74ACT175D-MC74ACT175N
Quad D-Type Flip-Flop
-The MC74AC/ACT175 is a high-speed quad D flip-flop. The device is useful for
general flip-flop requirements where clock and clear inputs are common. The
information on the D inputs is transferred to storage during the LOW-to-HIGH clock
MR is low.
The MC74AC/ACT175 consists of four edge-triggered D flip-flops with individual
D inputs and Q and Q outputs. The Clock (CP) and Master Reset (MR) are common
to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s
output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master
Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock
or Data inputs. The MC74AC/ACT175 is useful for applications where the Clock and
Master Reset are common to all storage elements. Outputs Source/Sink 24 mA ′ACT175 Has TTL Compatible Inputs
Pinout: 16-Lead Packages (Top View)VCC Q3 D3 D2 Q2 Q2 CP Q0 Q0 D0 D1 Q1 Q1 GND
PIN NAMESData Inputs
Clock Pulse Input
Master Reset Input
Outputs
Outputs
D0 – D3
Q0 – Q3
TRUTH TABLE
LOGIC SYMBOL
