74AC16373DL ,16-Bit Transparent D-Type Latches With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
74AC16373DLR ,16-Bit Transparent D-Type Latches With 3-State Outputs 54AC16373, 74AC16373 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCAS121B – MARCH 1990 – ..
74AC16374 ,16-BIT D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS (NON INVERTED)maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
74AC16374DLR ,16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 54AC16374, 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTSSCAS123B – MARCH 1 ..
74AC163M ,SYNCHRONOUS PRESETTABLE 4-BIT COUNTERABSOLUTE MAXIMUM RATINGS Symbol Parameter Value UnitV Supply Voltage-0.5 to +7 VCCV DC Input V ..
74AC163MTC ,Synchronous Presettable Binary CounterFunctional DescriptionThe AC/ACT163 counts in modulo-16 binary sequence.From state 15 (HHHH) it inc ..
74HC05 ,HEX INVERTERS WITH OPEN DRAIN OUTPUTSTC74HC05AP/AFl Ill‘vlel ' I‘. Ill‘vlelHEX |NVERTER(OPEN DRAIN)The TC74HCO5A is a high speed CMOS IN ..
74HC08DB ,74HC08; 74HCT08; Quad 2-input AND gate
74HC08DB ,74HC08; 74HCT08; Quad 2-input AND gate
74HC08DB ,74HC08; 74HCT08; Quad 2-input AND gate
74HC107D ,Dual JK flip-flop with reset; negative-edge triggerGENERAL DESCRIPTIONoperation.The 74HC/HCT107 are high-speed Si-gate CMOS devicesThe reset (nR) is a ..
74HC107N ,Dual JK flip-flop with reset; negative-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74AC16373DL-74AC16373DLR
16-Bit Transparent D-Type Latches With 3-State Outputs
Flow-Through Architecture OptimizesPCB Layout Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise EPIC (Enhanced-Performance Implanted
CMOS) 1-m m Process 500-mA Typical Latch-Up Immunity at
125°C Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
descriptionThe ’AC16373 are 16-bit transparent D-type
latches with 3-state outputs designed specifically
for driving highly capacitive or relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers. The device can be used as two 8-bit
latches or one 16-bit latch. When the latch-enable
(LE) input is high, the Q outputs follow the data (D)
inputs. When LE is taken low, the Q outputs are
latched at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
The 74AC16373 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin count
and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16373 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC16373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
