74AC163 ,SYNCHRONOUS PRESETTABLE 4-BIT COUNTERLOGIC DIAGRAM 2/1374AC163TIMING CHART 3/1374AC163
74AC16373DL ,16-Bit Transparent D-Type Latches With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
74AC16373DLR ,16-Bit Transparent D-Type Latches With 3-State Outputs 54AC16373, 74AC16373 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCAS121B – MARCH 1990 – ..
74AC16374 ,16-BIT D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS (NON INVERTED)maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
74AC16374DLR ,16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 54AC16374, 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTSSCAS123B – MARCH 1 ..
74AC163M ,SYNCHRONOUS PRESETTABLE 4-BIT COUNTERABSOLUTE MAXIMUM RATINGS Symbol Parameter Value UnitV Supply Voltage-0.5 to +7 VCCV DC Input V ..
74HC05 ,HEX INVERTERS WITH OPEN DRAIN OUTPUTSTC74HC05AP/AFl Ill‘vlel ' I‘. Ill‘vlelHEX |NVERTER(OPEN DRAIN)The TC74HCO5A is a high speed CMOS IN ..
74HC08DB ,74HC08; 74HCT08; Quad 2-input AND gate
74HC08DB ,74HC08; 74HCT08; Quad 2-input AND gate
74HC08DB ,74HC08; 74HCT08; Quad 2-input AND gate
74HC107D ,Dual JK flip-flop with reset; negative-edge triggerGENERAL DESCRIPTIONoperation.The 74HC/HCT107 are high-speed Si-gate CMOS devicesThe reset (nR) is a ..
74HC107N ,Dual JK flip-flop with reset; negative-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74AC163
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
1/13April 2001 HIGH SPEED:
fMAX = 200MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 8μA(MAX.) at TA =25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 163 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74AC163 is an advanced high-speed CMOS
SYNCRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS tecnology. It is a
4 bit binary counter with Synchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
Enable Input (LOAD), Count Enable Input (PE)
and Count Enable Carry Input (TE), determine the
mode of operation as shown in the Truth Table. A
LOW signal on CLEAR overrides counting and
parallel loading and sets all outputs on LOW state
on the next rising edge of CLOCK. A LOW signal
on LOAD overrides counting and allows
information on Parallel Data inputs to be loaded
into the flip-flop on the next rising edge of CLOCK.
With LOAD and CLEAR HIGH, PE and TE permit
counting when both are HIGH. Conversely, a
LOW signal on either PE and TE inhibits counting.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74AC163SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74AC163
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care; A, B, C, D; Logic level of data input; CARRY OUT : TE x QA x QB x QC x QD
LOGIC DIAGRAM
74AC1633/13
TIMING CHART
74AC1634/13
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 30% to 70% of VCC
74AC1635/13
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
74AC1636/13
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
74AC1637/13
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAYS, COUNT MODE (f=1MHz; 50% duty cycle)
