74AC138SCX ,1-of-8 Decoder/DemultiplexerFunctional Description Logic DiagramThe AC/ACT138 high-speed 1-of-8 decoder/demultiplexeraccepts th ..
74AC138SJ ,1-of-8 Decoder/Demultiplexer74AC138 • 74ACT138 1-of-8 Decoder/DemultiplexerNovember 1988Revised July 200374AC138 74ACT1381-of ..
74AC138SJ ,1-of-8 Decoder/DemultiplexerFeaturesThe AC/ACT138 is a high-speed 1-of-8 decoder/demulti-
74AC138MTC-74AC138MTCX-74AC138PC-74AC138SCX-74AC138SJ-74AC138SJX-74ACT138PC-74ACT138SC-74ACT138SCX-74ACT138SJ-74ACT138SJX
1-of-8 Decoder/Demultiplexer
74AC138 • 74ACT138 1-of-8 Decoder/Demultiplexer November 1988 Revised July 2003 74AC138 74ACT138 1-of-8 Decoder/Demultiplexer General Description Features The AC/ACT138 is a high-speed 1-of-8 decoder/demulti-I reduced by 50% CC plexer. This device is ideally suited for high-speed bipolar Demultiplexing capability memory chip select address decoding. The multiple input Multiple input enable for easy expansion enables allow parallel expansion to a 1-of-24 decoder Active LOW mutually exclusive outputs using just three AC/ACT138 devices or a 1-of-32 decoder using four AC/ACT138 devices and one inverter.Outputs source/sink 24 mA ACT138 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC138SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74AC138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC138MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC138PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT138SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACT138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT138PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Logic Symbols IEEE/IEC Pin Descriptions Pin Names Description A –A Address Inputs 0 2 E –E Enable Inputs 1 2 E Enable Input 3 O –O Outputs 0 7 FACT is a trademark of . © 2003 DS009925
