74AC11074DR ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Presetmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
74AC11074N ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Presetmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
74AC11074N ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset SCAS499A − DECEMBER 1986 − REVISED ..
74AC11112 ,DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
74AC11112N ,Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP -40 to 85
74AC11138N ,3-Line to 8-Line Decoders/Demultiplexers SCAS042B − MAY 1988 − REVISED APRIL 1996D, N, OR PW PACKA ..
74H1G66S ,SINGLE BILATERAL SWITCHABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Supply Voltage -0.5 to +13 VCCV DC Input Volta ..
74H21 , DUAL 4-INPUT POSITIVE AND GATE
74H21DC , DUAL 4-INPUT POSITIVE AND GATE
74HC00 ,QUADRUPLE 2-INPUT NAND GATESMAXIMUM RATINGSÎÎ Symbol Parameter Value UnitThis device contains protectioncircuitry to guard aga ..
74HC00BQ ,Quad 2-input NAND gate
74HC00DB ,Quad 2-input NAND gate
74AC11074-74AC11074DR-74AC11074N
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
125°C Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
descriptionThis device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)
or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR
are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the
outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is
not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may
be changed without affecting the levels at the outputs.
The 74AC11074 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
2PRE
1CLR
VCC
2CLR
2CLK
