74ACT10SCX ,Triple 3-Input NAND GateFeaturesThe AC/ACT10 contains three, 3-input NAND gates.
74AC109MTCX-74AC109PC-74AC109SC-74AC109SCX-74AC109SJ-74AC109SJX-74ACT109PC-74ACT109SC-74ACT109SCX
Dual JK Positive Edge-Triggered Flip-Flop
74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop November 1988 Revised August 2000 74AC109 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two high-speed completelyI reduced by 50% CC independent transition clocked JK flip-flops. The clocking Outputs source/sink 24 mA operation is independent of rise and fall times of the clock ACT109 has TTL-compatible inputs waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to S (Set) sets Q to HIGH level D LOW input to C (Clear) sets Q to LOW level D Clear and Set are independent of clock Simultaneous LOW on C and S makes D D both Q and Q HIGH Ordering Code: Order Number Package Number Package Description 74AC109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74AC109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC109MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC109PC N16E 16-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74AC109MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description J , J , K , K Data Inputs 1 2 1 2 CP , CP Clock Pulse Inputs 1 2 C , C Direct Clear Inputs D1 D2 S , S Direct Set Inputs D1 D2 Q , Q , Q , Q Outputs 1 2 1 2 FACT is a trademark of . © 2000 DS009923
